A survey on mapping and scheduling techniques for 3D Network-on-chip
SP Kaur, M Ghose, A Pathak, R Patole - Journal of Systems Architecture, 2024 - Elsevier
Abstract Network-on-chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …
AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip
Vertical die stacking of 3D Networks-on-Chip (3D NoCs) is enabled using inter-layer
Through-Silicon-Via (TSV) links. However, TSV technology suffers from low reliability and …
Through-Silicon-Via (TSV) links. However, TSV technology suffers from low reliability and …
Photonic networks-on-chip employing multilevel signaling: A cross-layer comparative study
VSP Karempudi, F Sunny, IG Thakkar… - ACM Journal on …, 2022 - dl.acm.org
Photonic network-on-chip (PNoC) architectures employ photonic links with dense
wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers …
wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers …
Approximate Priority Hybrid 3DNoC Buffered-Bufferless Router
This paper introduces a novel 3D NoC router that combines buffered and bufferless routing
with approximate priority comparison when deflecting flits. Our proposal is a modification of …
with approximate priority comparison when deflecting flits. Our proposal is a modification of …
Emerging trends in network on chip design for low latency and enhanced throughput applications
Traditionally Bus is used as an interconnection mechanism in many embedded systems.
The Bus often fails to accommodate the communication needs of such systems, as the need …
The Bus often fails to accommodate the communication needs of such systems, as the need …
Adaptive Experimental Design for Optimizing Combinatorial Structures
A Deshwal - 2024 - search.proquest.com
Many real-world scientific and engineering problems can be formulated as instances of goal-
driven adaptive experimental design, wherein candidate experiments are chosen …
driven adaptive experimental design, wherein candidate experiments are chosen …
[图书][B] Hardware Accelerators for Machine Learning: From 3D Manycore to Processing-in-Memory Architectures
AI Arka - 2022 - search.proquest.com
Big data applications such as-deep learning and graph analytics require hardware platforms
that are energy-efficient yet computationally powerful. 3D manycore architectures are the …
that are energy-efficient yet computationally powerful. 3D manycore architectures are the …
Fault Tolerant and Congestion-Aware Routing Algorithm in a Partially Connected 3D Network on Chip
S Yousefisadr, M Nouri - Advances in the Standards & Applied …, 2024 - journal.standard.ac.ir
Network-on-Chips (NoCs) have been accepted as a viable communication platform in many-
core systems. However, they possess high network latency and consume large power. In …
core systems. However, they possess high network latency and consume large power. In …
[HTML][HTML] Regional Power-Aware Routing for Partially-Connected 3D Network-on-Chip
M Moalemnia, HS Shahhoseini - Nashriyyah-i Muhandisi-i Barq …, 2023 - ijece.saminatech.ir
Network-on-chip provides an efficient communication platform for Systems-on-chip. The
static power consumption is an important issue in these networks. Switching the power …
static power consumption is an important issue in these networks. Switching the power …
[图书][B] Machine Learning to Scale Up Combinatorial Applications
FARR Chowdhury - 2020 - search.proquest.com
Combinatorial optimization problems arise in many scientific and engineering domains
including graph analytics, computational biology, natural language processing, and …
including graph analytics, computational biology, natural language processing, and …