Ramulator: A fast and extensible DRAM simulator

Y Kim, W Yang, O Mutlu - IEEE Computer architecture letters, 2015 - ieeexplore.ieee.org
Recently, both industry and academia have proposed many different roadmaps for the future
of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which …

DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator

S Li, Z Yang, D Reddy, A Srivastava… - IEEE Computer …, 2020 - ieeexplore.ieee.org
DRAM technology has developed rapidly in recent years. Several industrial solutions offer
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …

Balancing DRAM locality and parallelism in shared memory CMP systems

MK Jeong, DH Yoon, D Sunwoo… - … symposium on high …, 2012 - ieeexplore.ieee.org
Modern memory systems rely on spatial locality to provide high bandwidth while minimizing
memory device power and cost. The trend of increasing the number of cores that share …

A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC

MK Jeong, M Erez, C Sudanthi, N Paver - Proceedings of the 49th …, 2012 - dl.acm.org
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip
memory bandwidth is often the scarcest resource and requires careful allocation. Two of the …

Simulating DRAM controllers for future system architecture exploration

A Hansson, N Agarwal, A Kolli… - … Analysis of Systems …, 2014 - ieeexplore.ieee.org
Compute requirements are increasing rapidly in systems ranging from mobile devices to
servers. These, often massively parallel architectures, put increasing requirements on …

Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput

DH Yoon, MK Jeong, M Erez - Proceedings of the 38th annual …, 2011 - dl.acm.org
We propose adaptive granularity to combine the best of fine-grained and coarse-grained
memory accesses. We augment virtual memory to allow each page to specify its preferred …

The dynamic granularity memory system

DH Yoon, MK Jeong, M Sullivan, M Erez - ACM SIGARCH Computer …, 2012 - dl.acm.org
Chip multiprocessors enable continued performance scaling with increasingly many cores
per chip. As the throughput of computation outpaces available memory bandwidth, however …

Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications

I Hwang, J Lee, H Kang, G Lee, H Kim - Simulation Modelling Practice and …, 2024 - Elsevier
In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …

DRAMSys4. 0: a fast and cycle-accurate systemC/TLM-based DRAM simulator

L Steiner, M Jung, FS Prado, K Bykov… - … , Modeling, and Simulation …, 2020 - Springer
Abstract The simulation of DRAMs (Dynamic Random Access Memories) on system level
requires highly accurate models due to their complex timing and power behavior. However …

[PDF][PDF] Architectural techniques to enhance DRAM scaling

Y Kim - Ph. D. dissertation, Carnegie Mellon University, 2015 - kilthub.cmu.edu
For decades, main memory has enjoyed the continuous scaling of its physical substrate:
DRAM (DynamicRandomAccessMemory). Butnow, DRAMscalinghasreachedathreshold …