Fab-level discrete-event simulation is an important practical tool for the analysis and
optimization of semiconductor wafer fabricators. In such facilities, a clustered …

In semiconductor wafer fabricators (fabs), clustered photolithography tools (CPTs) are often
the bottleneck. With a focus on fab-level simulation, we propose a new class of equipment …

Cycle time requirements from prime or major customers contradict the ever-increasing
complexity of wafer fabrication. Lot size variations show up as significant cycle time …

The anticipated transition to 450 mm diameter wafers provides the semiconductor
manufacturing industry an opportunity to consider new equipment designs that address …

Linear and affine (Ax+ B) models are commonly used to model equipment throughput in
semiconductor wafer fabricator simulations. We endeavor to assess the quality of such …

For deterministic hybrid flow lines with multiple classes of customer and no overtaking, we
develop upper bounds on the customer departure times. For this general class of systems …

Due to the complexities of various modules and the cost of machinery involved in
semiconductor fabrication, it is vital to capture the efficiency of parts fabricated during the …