Energy efficient and side-channel secure cryptographic hardware for IoT-edge nodes

A Singh, N Chawla, JH Ko, M Kar… - IEEE Internet of …, 2018 - ieeexplore.ieee.org
Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-
Things edge devices. This paper explores the system level design space for an ultralow …

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

DS Kundi, A Aziz, N Ikram - Microprocessors and Microsystems, 2016 - Elsevier
In this paper, a unified Field Programmable Gate Array (FPGA) based Advanced Encryption
Standard (AES) encryptor/decryptor design is presented by proposing a symmetric ST-Box …

Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators

A Singh, M Kar, JH Ko… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
The power attack protection of encryption engines often comes at the expense of area,
power, and/or performance overheads making the design of a low-power and compact but …

A novel framework for secure file transmission using modified AES and MD5 algorithms

R Kumar, G Mahajan - International Journal of Information …, 2015 - inderscienceonline.com
With the tremendous growth of sensitive information on the internet, the security is getting
more and more important than even before. However, the growth of users has unfortunately …

Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON

A Singh, N Chawla, M Kar… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Design of ultra-lightweight but secure encryption engine is a key challenge for Internet-of-
Things (IOT) edge devices. We explore the architectural design space for datapath of 128-bit …

[PDF][PDF] Lightweight mixcolumn architecture for advanced encryption standard

KJJ Kumar, R Balasubramanian - International Journal of Computer …, 2016 - Citeseer
Lightweight cryptography is an interesting phenomenon that provides the perfect trade-off
among security, higher throughput, low-power consumption, and compactness. Designing …

An Improved Unified AES Implementation Using FPGA

B Prakash, V Gupta - International Journal of Embedded and Real …, 2022 - igi-global.com
Encryption is an essential process in electronic data transmission because it securely
protects the data from unauthorized access. In this digital era, information and its security are …

Multiobjective artificial bee colony algorithm for S-box optimization

G Qin, X Cheng, J Ma - 2015 International Conference on …, 2015 - atlantis-press.com
Substitution box (S-box) is an important nonlinear component in block cipher algorithms.
Evaluating the cryptographic properties of an S-box requires attention to criteria such as …

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

X Yang - 2016 - digitalcommons.fiu.edu
With industry expectations of billions of Internet-connected things, commonly referred to as
the IoT, we see a growing demand for high-performance on-chip bus architectures with the …

[PDF][PDF] Year of Publication: 2016

S Kumar, K Kumar - 2016 - academia.edu
The task of developing Intrusion Detection System (IDS) crucially depends on the
preprocessing along with selecting important data features of it. Another crucial factor is …