Efficient vector quantization of LPC parameters at 24 bits/frame
KK Paliwal, BS Atal - IEEE transactions on speech and audio …, 1993 - ieeexplore.ieee.org
For low bit rate speech coding applications, it is important to quantize the LPC parameters
accurately using as few bits as possible. Though vector quantizers are more efficient than …
accurately using as few bits as possible. Though vector quantizers are more efficient than …
Processor design for soft errors: Challenges and state of the art
Today, soft errors are one of the major design technology challenges at and beyond the
22nm technology nodes. This article introduces the soft error problem from the perspective …
22nm technology nodes. This article introduces the soft error problem from the perspective …
Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology
K Lilja, M Bounasser, SJ Wen, R Wong… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
Alpha, neutron, and heavy-ion single-event measurements were performed on both high-
performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The …
performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The …
[PDF][PDF] Technology scaling and soft error reliability
LW Massengill, BL Bhuva… - 2012 IEEE …, 2012 - reliablemicrosystems.com
Technology Scaling and Soft Error Reliability Page 1 Technology Scaling and Soft Error
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …
Design and evaluation of radiation-hardened standard cell flip-flops
O Schrape, M Andjelković… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-
effective solution for space applications. In this paper we demonstrate how a standard non …
effective solution for space applications. In this paper we demonstrate how a standard non …
Tolerating soft errors in deep learning accelerators with reliable on-chip memory designs
A Azizimazreah, Y Gu, X Gu… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Deep learning neural network (DNN) accelerators have been increasingly deployed in many
fields recently, including safety-critical applications such as autonomous vehicles and …
fields recently, including safety-critical applications such as autonomous vehicles and …
Comprehensive analysis of sequential and combinational soft errors in an embedded processor
M Ebrahimi, A Evans, MB Tahoori… - … on Computer-Aided …, 2015 - ieeexplore.ieee.org
Radiation-induced soft errors have become a key challenge in advanced commercial
electronic components and systems. We present the results of a soft error rate (SER) …
electronic components and systems. We present the results of a soft error rate (SER) …
32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches
KP Rodbell, DF Heidel, JA Pellish… - … on Nuclear Science, 2011 - ieeexplore.ieee.org
Single event upset (SEU) experimental heavy ion data and modeling results for CMOS,
silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel …
silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel …
Frequency dependence of alpha-particle induced soft error rates of flip-flops in 40-nm CMOS technology
In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a
function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops-an …
function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops-an …
Single-event tolerant flip-flop design in 40-nm bulk CMOS technology
In this paper, the radiation response of a single-event tolerant flip-flop design named the
Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the …
Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the …