Field programmable gate array applications—A scientometric review

J Ruiz-Rosero, G Ramirez-Gonzalez, R Khanna - Computation, 2019 - mdpi.com
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs

MK Papamichael, JC Hoe - Proceedings of the ACM/SIGDA international …, 2012 - dl.acm.org
An FPGA is a peculiar hardware realization substrate in terms of the relative speed and cost
of logic vs. wires vs. memory. In this paper, we present a Network-on-Chip (NoC) design …

[图书][B] Efficient microarchitecture for network-on-chip routers

DU Becker - 2012 - search.proquest.com
Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …

SynFull: Synthetic traffic models capturing cache coherent behaviour

M Badr, NE Jerger - ACM SIGARCH Computer Architecture News, 2014 - dl.acm.org
Modern and future many-core systems represent complex architectures. The communication
fabrics of these large systems heavily influence their performance and power consumption …

Revisiting the high-performance reconfigurable computing for future datacenters

Q Ijaz, EB Bourennane, AK Bashir, H Asghar - Future Internet, 2020 - mdpi.com
Modern datacenters are reinforcing the computational power and energy efficiency by
assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale …

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

A Monemi, JW Tang, M Palesi, MN Marsono - Microprocessors and …, 2017 - Elsevier
Abstract Network-on-chip (NoC) is an emerging interconnect infrastructure to address the
scalability limitation of conventional shared bus architecture for many-core system-on-chip …

Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga

TV Chu, S Sato, K Kise - ACM Transactions on Reconfigurable …, 2017 - dl.acm.org
Modeling and simulation/emulation play a major role in research and development of novel
Networks-on-Chip (NoCs). However, conventional software simulators are so slow that …

Performance evaluation of noc-based multicore systems: From traffic analysis to noc latency modeling

Z Qian, P Bogdan, CY Tsui, R Marculescu - ACM Transactions on Design …, 2016 - dl.acm.org
In this survey, we review several approaches for predicting performance of Network-on-Chip
(NoC)-based multicore systems, starting from the traffic models to the complex NoC models …

Ultra-fast NoC emulation on a single FPGA

T Van Chu, S Sato, K Kise - 2015 25th International Conference …, 2015 - ieeexplore.ieee.org
Network-on-Chip (NoC) has become the de facto on-chip communication architecture for
many-core systems. This paper proposes novel methods for emulating large-scale NoC …

Scaling datacenter accelerators with compute-reuse architectures

A Fuchs, D Wentzlaff - 2018 ACM/IEEE 45th Annual …, 2018 - ieeexplore.ieee.org
Hardware specialization is commonly used in datacenters to ameliorate the nearing end of
CMOS technology scaling. While offering superior performance and energy-efficiency …