A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
CH Chang, J Gu, M Zhang - IEEE Transactions on very large …, 2005 - ieeexplore.ieee.org
The general objective of our work is to investigate the area and power-delay performances
of low-voltage full adder cells in different CMOS logic styles for the predominating tree …
of low-voltage full adder cells in different CMOS logic styles for the predominating tree …
Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers
Approximate multipliers attract a large interest in the scientific literature that proposes
several circuits built with approximate 4-2 compressors. Due to the large number of …
several circuits built with approximate 4-2 compressors. Due to the large number of …
Approximate multipliers based on new approximate compressors
Approximate computing is an emerging trend in digital design that trades off the requirement
of exact computation for improved speed and power performance. This paper proposes …
of exact computation for improved speed and power performance. This paper proposes …
A review, classification, and comparative evaluation of approximate arithmetic circuits
Often as the most important arithmetic modules in a processor, adders, multipliers, and
dividers determine the performance and energy efficiency of many computing tasks. The …
dividers determine the performance and energy efficiency of many computing tasks. The …
High-speed Booth encoded parallel multiplier design
WC Yeh, CW Jen - IEEE transactions on computers, 2000 - ieeexplore.ieee.org
This paper presents a design methodology for high-speed Booth encoded parallel multiplier.
For partial product generation, we propose a new modified Booth encoding (MBE) scheme …
For partial product generation, we propose a new modified Booth encoding (MBE) scheme …
Energy and area efficient imprecise compressors for approximate multiplication at nanoscale
Approximate computing is a new paradigm for designing energy-efficient integrated circuits
at the nanoscale. In this paper, we propose efficient imprecise 4: 2 and 5: 2 compressors by …
at the nanoscale. In this paper, we propose efficient imprecise 4: 2 and 5: 2 compressors by …
A 13.34 μW Event-Driven Patient-Specific ANN Cardiac Arrhythmia Classifier for Wearable ECG Sensors
Artificial neural network (ANN) and its variants are favored algorithm in designing cardiac
arrhythmia classifier (CAC) for its high accuracy. However, the implementation of ultralow …
arrhythmia classifier (CAC) for its high accuracy. However, the implementation of ultralow …
Understanding broadcast based peer review on open source software projects
Software peer review has proven to be a successful technique in open source software
(OSS) development. In contrast to industry, where reviews are typically assigned to specific …
(OSS) development. In contrast to industry, where reviews are typically assigned to specific …
Low-power approximate unsigned multipliers with configurable error recovery
Approximate circuits have been considered for applications that can tolerate some loss of
accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic …
accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic …
High-performance low-power left-to-right array multiplier design
Z Huang, MD Ercegovac - IEEE Transactions on computers, 2005 - ieeexplore.ieee.org
We present a high-performance low-power design of linear array multipliers based on a
combination of the following techniques: signal flow optimization in [3: 2] adder array for …
combination of the following techniques: signal flow optimization in [3: 2] adder array for …