The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …

A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz
bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital …

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an …

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …

This paper presents the first fully integrated 24-GHz phased-array transmitter designed
using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS …

A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-
GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude …

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a
stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to …

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital
converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to …

This paper describes the key technology and circuit design issues facing the design of an
efficient linear RF CMOS power amplifier for modern communication standards …