[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments
J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …
digital processing of analog signals encoded in time. Since design of time-mode circuits …
Re-thinking analog integrated circuits in digital terms: A new design concept for the IoT era
A steady trend towards the design of mostly-digital and digital-friendly analog circuits,
suitable to integration in mainstream nanoscale CMOS by a highly automated design flow …
suitable to integration in mainstream nanoscale CMOS by a highly automated design flow …
Challenges and opportunities toward fully automated analog layout design
Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated
task due to the high design flexibility and sensitive circuit performance. Compared with the …
task due to the high design flexibility and sensitive circuit performance. Compared with the …
Design of digital OTAs with operation down to 0.3 V and nW power for direct harvesting
In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for
energy-and area-constrained systems are modeled and analyzed from a design viewpoint …
energy-and area-constrained systems are modeled and analyzed from a design viewpoint …
A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection …
This paper presents a fully synthesizable phase-locked loop (PLL) based on injection
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog …
Low-voltage, low-area, nW-power CMOS digital-based biosignal amplifier
This paper presents the operation principle and the silicon characterization of a power
efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational …
efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational …
Rail-to-rail dynamic voltage comparator scalable down to pW-range power and 0.15-V supply
An ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator solely based on
digital standard cells is presented. Thanks to its digital nature, the comparator can be …
digital standard cells is presented. Thanks to its digital nature, the comparator can be …
A 69.5 mW 20 GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32 nm CMOS SOI
A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded
time-to-digital converter to sense timing skew, and the randomness of process mismatch is …
time-to-digital converter to sense timing skew, and the randomness of process mismatch is …
Fully synthesizable low-area analogue-to-digital converters with minimal design effort based on the dyadic digital pulse modulation
In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-
Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for …
Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for …
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators
YS Shu - 2012 Symposium on VLSI Circuits (VLSIC), 2012 - ieeexplore.ieee.org
A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021 mm 2.
Dynamic comparators with digitally controlled built-in offset are realized with imbalanced …
Dynamic comparators with digitally controlled built-in offset are realized with imbalanced …