An overview and classification of thermal-aware scheduling techniques for multi-core processing systems

HF Sheikh, I Ahmad, Z Wang, S Ranka - … Computing: Informatics and …, 2012 - Elsevier
Thermal-aware scheduling of parallel jobs is becoming an increasingly critical issue in
software design for computing platforms ranging from embedded systems to large servers …

Affinity-based thread and data mapping in shared memory systems

M Diener, EHM Cruz, MAZ Alves, POA Navaux… - ACM Computing …, 2016 - dl.acm.org
Shared memory architectures have recently experienced a large increase in thread-level
parallelism, leading to complex memory hierarchies with multiple cache memory levels and …

Thread reinforcer: Dynamically determining number of threads via os level monitoring

KK Pusukuri, R Gupta… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
It is often assumed that to maximize the performance of a multithreaded application, the
number of threads created should equal the number of cores. While this may be true for …

Understanding the thermal implications of multi-core architectures

P Chaparro, J Gonzáles, G Magklis… - … on Parallel and …, 2007 - ieeexplore.ieee.org
Multi-core architectures are becoming the main design paradigm for current and future
processors. The main reason is that multi-core designs provide an effective way of …

Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems

G Liu, J Park, D Marculescu - 2013 IEEE 31st international …, 2013 - ieeexplore.ieee.org
This paper addresses the problem of dynamic thread mapping in heterogeneous many-core
systems via an efficient algorithm that maximizes performance under power constraints …

Temperature-aware DVFS for hard real-time applications on multicore processors

V Hanumaiah, S Vrudhula - IEEE Transactions on Computers, 2011 - ieeexplore.ieee.org
This paper addresses the problem of determining the feasible speeds and voltages of
multicore processors with hard real-time and temperature constraints. This is an important …

Agileregulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture

G Yan, Y Li, Y Han, X Li, M Guo… - … Symposium on High …, 2012 - ieeexplore.ieee.org
The widening gap between the fast-increasing transistor budget but slow-growing power
delivery and system cooling capability calls for novel architectural solutions to boost energy …

Leveraging core specialization via OS scheduling to improve performance on asymmetric multicore systems

JC Saez, A Fedorova, D Koufaty, M Prieto - ACM Transactions on …, 2012 - dl.acm.org
Asymmetric multicore processors (AMPs) consist of cores with the same ISA (instruction-set
architecture), but different microarchitectural features, speed, and power consumption …

Migrating threads between asymmetric cores in a multiple core processor

SS Jahagirdar, V George, I Sodhi - US Patent 9,727,388, 2017 - Google Patents
Some implementations provide techniques and arrangements to migrate threads from a first
core of a processor to a second core of the processor. For example, some implementations …

Performance implications of cache affinity on multicore processors

V Kazempour, A Fedorova, P Alagheband - Euro-Par 2008–Parallel …, 2008 - Springer
Cache affinity between a process and a processor is observed when the processor cache
has accumulated some amount of the process state, ie, data or instructions. Cache affinity is …