Vertically-grown TFETs: an extensive analysis
AS Geege, TSA Samuel - Silicon, 2023 - Springer
TFET is an exciting device for ultra-low and low power implementations since it improves
electrical performance while also providing steeper switching ratio. This study encloses with …
electrical performance while also providing steeper switching ratio. This study encloses with …
Investigation of N+ SiGe juntionless vertical TFET with gate stack for gas sensing application
In this work, a novel N+ SiGe delta-doped gate stacked junctionless vertical tunnel field
transistor (N+ SiGe gate staked JL-VTFET) is proposed and investigated with its electrical …
transistor (N+ SiGe gate staked JL-VTFET) is proposed and investigated with its electrical …
Drain dielectric pocket engineering: its impact on the electrical performance of a hetero-structure tunnel FET
In this paper, a simulated Si0. 6Ge0. 4/Si hetero-structure double gate tunneling FET with
drain dielectric pocket (DDP-SiGe-TFET) is reported for the first time. The high-k (HfO2) …
drain dielectric pocket (DDP-SiGe-TFET) is reported for the first time. The high-k (HfO2) …
Design and analysis of ferro electric-tunneling junction-VTFET for RF/analog and linear application
S Singh - Silicon, 2022 - Springer
In this paper a new ferro material embedded structure is introduced between the tunneling
junction to gain and improve ON/OFF current ratio with steeper subthreshold slope. Various …
junction to gain and improve ON/OFF current ratio with steeper subthreshold slope. Various …
Design and analysis of a double gate SiGe/Si tunnel FET with unique inner-gate engineering
An inner-gate engineered double gate heterostructure tunnel field effect transistor (SiGe/Si-
IGTFET) has been presented. The inner-gate is grown at the center of the Si 0.6 Ge 0.4/Si …
IGTFET) has been presented. The inner-gate is grown at the center of the Si 0.6 Ge 0.4/Si …
Two dimensional modeling of dual material double gate TFET in stacked hetero-dielectrics with split high-K materials
this article develops the analytical modelling of a dual material double gate TFET including
gate engineering using a hetero–dielectric gate stack with split high K dielectrics. The …
gate engineering using a hetero–dielectric gate stack with split high K dielectrics. The …
Modeling and simulation analysis hetero junction doping less vertical TFET for biomedical application
In this manuscript, the physical modeling of the hetero junction doping less vertical TFET
(HJD-VTFET) is carried out. The mathematical relations of the surface potential are …
(HJD-VTFET) is carried out. The mathematical relations of the surface potential are …
Performance analysis of different Tunnel Field Effect Transistors (TFET) device structures with their Challenges
S Gupta, S Wariya - 2021 8th International Conference on …, 2021 - ieeexplore.ieee.org
Tunnel Field Effect Transistor (TFET) is emerging as a suitable device to operate at a very
low power. TFET overcomes the challenges faced by MOSFET based on its different …
low power. TFET overcomes the challenges faced by MOSFET based on its different …
Dual Source Vertical TFET Channel Overlapped Structure with Enhanced RF/Analog Performance for Low-Power-Applications
This paper emphasizes evaluating the structure and performance of a Dual Source Vertical
Tunnel Field-Effect Transistor (DS-VTFET) at the device level. This involves the analysis of …
Tunnel Field-Effect Transistor (DS-VTFET) at the device level. This involves the analysis of …
Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application
A Yadav, S Wairya - 2022 - researchsquare.com
An ultimate requirement of the less power, high speed and energy efficient analog to digital
converters (ADCs) have given immense popularity to dual stage positive feedback based …
converters (ADCs) have given immense popularity to dual stage positive feedback based …