Survey of turbo, LDPC, and polar decoder ASIC implementations

S Shao, P Hailes, TY Wang, JY Wu… - … Surveys & Tutorials, 2019 - ieeexplore.ieee.org
Channel coding may be viewed as the best-informed and most potent component of cellular
communication systems, which is used for correcting the transmission errors inflicted by …

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

M Kingston Roberts, S Kumari… - International Journal of …, 2021 - Wiley Online Library
Information theory coding is an impressive and most celebrated field of research that has
spawned numerous extremely important solutions to the intractable problems of secure data …

High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule

S Kumawat, R Shrestha, N Daga… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC
code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11 …

A fully parallel LDPC decoder architecture using probabilistic min-sum algorithm for high-throughput applications

CC Cheng, JD Yang, HC Lee… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a normalized probabilistic min-sum algorithm for low-density parity-
check (LDPC) codes, where a probabilistic second minimum value, instead of the true …

An efficient multi-standard LDPC decoder design using hardware-friendly shuffled decoding

YL Ueng, BJ Yang, CJ Yang, HC Lee… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder
architecture using a shuffled decoding algorithm, where variable nodes are divided into …

Two informed dynamic scheduling strategies for iterative LDPC decoders

HC Lee, YL Ueng, SM Yeh… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
When residual belief-propagation (RBP), which is a kind of informed dynamic scheduling
(IDS), is applied to low-density parity-check (LDPC) codes, the convergence speed in error …

An efficient layered decoding architecture for nonbinary QC-LDPC codes

YL Ueng, CY Leong, CJ Yang… - … on Circuits and …, 2011 - ieeexplore.ieee.org
Compared to binary low-density parity-check (LDPC) codes, nonbinary LDPC codes have
better error performance when the code length is moderate. This paper presents an efficient …

Optimization techniques for the efficient implementation of high-rate layered QC-LDPC decoders

HC Lee, MR Li, JK Hu, PC Chou… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be
reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) …

A high-throughput trellis-based layered decoding architecture for non-binary LDPC codes using max-log-QSPA

YL Ueng, KH Liao, HC Chou… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper presents a high-throughput decoder architecture for non-binary low-density parity-
check (LDPC) codes, where the q-ary sum-product algorithm (QSPA) in the log domain is …

An iterative detection and decoding receiver for LDPC-coded MIMO systems

WC Sun, WH Wu, CH Yang… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents a high-throughput, area-efficient and energy-efficient iterative detection
and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input …