Monolithically stacked two layers of a-IGZO-based transistors upon a-IGZO-based analog/logic circuits

W Lu, C Lu, G Yang, M Liu, K Chen… - … on Electron Devices, 2023 - ieeexplore.ieee.org
In this work, back end of line (BEOL)-compatible amorphous indium–gallium–zinc oxide (a-
IGZO) transistors are monolithically stacked on top of first-layer a-IGZO-based analog/digital …

Next-generation high-density PCB development by fan-out RDL technology

MK Shih, YW Huang, GS Lin - IEEE Transactions on Device …, 2022 - ieeexplore.ieee.org
High-density interconnect (HDI) printed circuit boards (PCBs) are in high demand for
smartphones, particularly those with fifth generation (5G) functionality, due to their smaller …

Large-body-sized glass-based active interposer for high-performance computing

S Ravichandran, M Kathaperumal… - 2020 IEEE 70th …, 2020 - ieeexplore.ieee.org
This paper presents a next generation glass-based active interposer with 2 micron polymer
RDL. Passive 2.5 D interposers have become a mainstream solution to address the …

Silicon reliability characterization of Intel's Foveros 3D integration technology for logic-on-logic die stacking

C Prasad, S Chugh, H Greve, I Ho… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
This work presents silicon reliability characterization of Intel's Foveros three-dimensional
(3D) logic-on-logic stacking technology implemented on the 22FFL process node …

Enhancing interconnection network topology for chiplet-based systems: An automated design framework

Z Cao, Q Liu, Z Wan, W Zhang, K Song, W Liu - Future Generation …, 2025 - Elsevier
Chiplet-based systems integrate discrete chips on an interposer and use the interconnection
network to enable communication between different components. The topology of the …

Wearable SiPM-based NIRS interface integrated with pulsed laser source

S Saha, Y Lu, F Lesage… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
We present the design of a miniaturized probe integrating silicon photomultiplier and light-
pulsing electronics in a single 2× 2 mm 2 complementary metal-oxide-semiconductor …

Enhanced Fabrication and Assembly of 3-D Chiplets Based on Active Interposer with Frontside Via-last TSVs

C Liao, H He, X Wang, R Cao, L Chen… - IEEE Transactions …, 2024 - ieeexplore.ieee.org
The development of semiconductors, driven by artificial intelligence (AI) and fifth-generation
technology (5G) technologies, has posed challenges in advanced packaging. To address …

Development of 4 die stack module using Hybrid bonding approach

SC Chong, JAK Yuen, VN Sekhar… - 2023 IEEE 73rd …, 2023 - ieeexplore.ieee.org
Die stacking is commonly used in memory modules. Solder micro-bumps and through
silicon via (TSVs) are common interconnects, and it may not viable or suitable for device that …

Defect localization in through-Si-interposer based 2.5 D ICS

SBN Gourikutty, YM Chow, J Alton… - 2020 IEEE 70th …, 2020 - ieeexplore.ieee.org
Advanced packaging solutions using Through Silicon Interposers (TSI) are an attractive
option to create 2.5 D ICs. In many applications such as GPU and FPGA, 2.5 D ICs can …

FOWLP and Si-Interposer for High-Speed Photonic Packaging

LT Guan, EWL Ching, JM Ching… - 2021 IEEE 71st …, 2021 - ieeexplore.ieee.org
A FOWLP and a Si-Interposer integration platform for Electronic IC (EIC) and Photonic IC
(PIC) are described here. These two platforms are capable to support high-speed integration …