This paper conducts a comprehensive study on existing circuit optimization techniques
against NBTI, degradation mechanism that has become a critical reliability issue for nano …

This paper describes architectural extensions for a dynamically scheduled processor, so that
it can be used in three different operation modes, ranging from high-performance, to high …

This paper describes architectural extensions for a dynamically scheduled processor, in
order to make it almost completely fault-tolerant against single event upsets. The base …

With the rapid development of semiconductor technology, chip integration is getting beyond
imagination. Aging has become one of the main threats to circuit reliability. In order to …

For several years, many authors have predicted that nano-scale integrated devices and
circuits will have a rising sensitivity to both transient and permanent faults effects …

This paper deals with the design of embedded systems for safety-critical applications, where
both fault-tolerance and real-time requirements should be taken into account at the same …

Os avanços tecnológicos em circuitos integrados tem como foco principal a redução da
dimensão dos transistores. No entanto, esta redução traz consequências indesejáveis …

This article describes architectural extensions for a dynamically scheduled processor to
enable three different operation modes, ranging from high-performance, to high-reliability …

Non-volatile memory area occupies a large portion of the area of a chip in an embedded
system. Such memories are prone to manufacturing faults, retention faults, and aging faults …

In this paper we evaluate the feasibility of software-based repair for program (NOR flash)
memories in tiny embedded systems. Often, in such systems, it is very typical that not the full …