In a particular illustrative embodiment, a method of fabricating a semiconductor device is
disclosed that includes forming a metal layer over a device substrate, forming a via in …

Dynamic power consumption is an ongoing concern for integrated circuit (IC) devices,
especially with the ever-in creasing clock frequencies used in Synchronous IC devices …

A clock gating latch, a method of gating a clock signal and an integrating circuit
incorporating the clock gating latch or the method. In one embodiment, the clock gating latch …

Methods, apparatuses, and computer-readable storage media are disclosed for reducing
power by reducing hardware-thread toggling in a multi-threaded processor. In a particular …

In an aspect of the disclosure, a clock-gating cell includes an enable module and a latch
module. The enable module includes a NOR gate that receives an enable module input and …

An apparatus is provided which comprises: a clock node; a test node; an enable node; and
an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable …

Inventive aspects include an integrated clock gater (ICG) circuit having clocked
complimentary voltage switched logic (CICG) that delivers high performance while …

A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that
decodes the plurality of input signals to produce a result at a first node, the result is …

An apparatus for an integrated clock gating cell is provided. The apparatus includes a logic
gate that receives an unbuffered enable signal (E), a scan test enable signal (SE), and …

(57) ABSTRACT A dynamic decode circuit for decoding a plurality of input signals comprises
a decoder that decodes the plurality of input signals to produce a result at a first node, the …