A digital audio system including a digital phase-locked-loop circuit for generating a pulse-
width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width …

(57) ABSTRACT A memory cell that may be used for computation and processing array
using the memory cell are capable to performing a logic operation including a boolean AND …

H03L7/089—Details of the phase-locked loop concerning mainly the frequency-or phase-
detection arrangement including the filtering or amplification of its output signal the phase or …

Abstract Systems and methods are disclosed relating to fields of clock/data acquisition or
handling, such as clock/data locking and the like. In one exemplary implementation, phase …

A memory cell that may be used for computation and processing array using the memory cell
are capable to performing a logic operation including a boolean AND, a boolean OR, a …

A memory cell and processing array that has a plurality of memory are capable of performing
logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic …

A memory cell that may be used for computation and processing array using the memory cell
are capable to performing a logic operation including a boolean AND, a boolean OR, a …

The embodiments herein generally relate to electronics circuits, and, more particularly, to a
digital phase-locked loop (PLL) electronic circuit. 2. Description of the Related Art Phase …

A read register is provided that captures and stores the read result on a read bit line
connected to a set of computational memory cells. The read register may be implemented in …

A read and write data processing apparatus and method associated with computational
memory cells formed as a memory/processing array provides the ability to inhibit writes in …