Error characterization, mitigation, and recovery in flash-memory-based solid-state drives
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …
continuously increased and cost has continuously decreased over decades. This positive …
Recnmp: Accelerating personalized recommendation with near-memory processing
Personalized recommendation systems leverage deep learning models and account for the
majority of data center AI cycles. Their performance is dominated by memory-bound sparse …
majority of data center AI cycles. Their performance is dominated by memory-bound sparse …
Exploiting correcting codes: On the effectiveness of ecc memory against rowhammer attacks
Given the increasing impact of Rowhammer, and the dearth of adequate other hardware
defenses, many in the security community have pinned their hopes on error-correcting code …
defenses, many in the security community have pinned their hopes on error-correcting code …
Memory errors in modern systems: The good, the bad, and the ugly
Several recent publications have shown that hardware faults in the memory subsystem are
commonplace. These faults are predicted to become more frequent in future systems that …
commonplace. These faults are predicted to become more frequent in future systems that …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
A study of DRAM failures in the field
V Sridharan, D Liberty - SC'12: Proceedings of the International …, 2012 - ieeexplore.ieee.org
Most modern computer systems use dynamic random access memory (DRAM) as a main
memory store. Recent publications have confirmed that DRAM errors are a common source …
memory store. Recent publications have confirmed that DRAM errors are a common source …
A survey of architectural techniques for DRAM power management
S Mittal - … Journal of High Performance Systems Architecture, 2012 - inderscienceonline.com
Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been estimated …
have dramatically increased the power consumption of main memory. It has been estimated …
A survey of techniques for improving error-resilience of DRAM
S Mittal, MS Inukonda - Journal of Systems Architecture, 2018 - Elsevier
Aggressive process scaling and increasing demands of performance/cost efficiency have
exacerbated the incidences and impact of errors in DRAM systems. Due to this …
exacerbated the incidences and impact of errors in DRAM systems. Due to this …
Design and optimization of low voltage high performance dual threshold CMOS circuits
Reduction in leakage power has become an important concern in low voltage, low power
and high performance applications. In this paper, we use dual threshold technique to reduce …
and high performance applications. In this paper, we use dual threshold technique to reduce …
Synergy: Rethinking secure-memory design for error-correcting memories
Building trusted data-centers requires resilient memories which are protected from both
adversarial attacks and errors. Unfortunately, the state-of-the-art memory security solutions …
adversarial attacks and errors. Unfortunately, the state-of-the-art memory security solutions …