Error characterization, mitigation, and recovery in flash-memory-based solid-state drives

Y Cai, S Ghose, EF Haratsch, Y Luo… - Proceedings of the …, 2017 - ieeexplore.ieee.org
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …

Recnmp: Accelerating personalized recommendation with near-memory processing

L Ke, U Gupta, BY Cho, D Brooks… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Personalized recommendation systems leverage deep learning models and account for the
majority of data center AI cycles. Their performance is dominated by memory-bound sparse …

Exploiting correcting codes: On the effectiveness of ecc memory against rowhammer attacks

L Cojocar, K Razavi, C Giuffrida… - 2019 IEEE Symposium …, 2019 - ieeexplore.ieee.org
Given the increasing impact of Rowhammer, and the dearth of adequate other hardware
defenses, many in the security community have pinned their hopes on error-correcting code …

Memory errors in modern systems: The good, the bad, and the ugly

V Sridharan, N DeBardeleben, S Blanchard… - ACM SIGARCH …, 2015 - dl.acm.org
Several recent publications have shown that hardware faults in the memory subsystem are
commonplace. These faults are predicted to become more frequent in future systems that …

Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization

KK Chang, A Kashyap, H Hassan, S Ghose… - Proceedings of the …, 2016 - dl.acm.org
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …

A study of DRAM failures in the field

V Sridharan, D Liberty - SC'12: Proceedings of the International …, 2012 - ieeexplore.ieee.org
Most modern computer systems use dynamic random access memory (DRAM) as a main
memory store. Recent publications have confirmed that DRAM errors are a common source …

A survey of architectural techniques for DRAM power management

S Mittal - … Journal of High Performance Systems Architecture, 2012 - inderscienceonline.com
Recent trends of CMOS technology scaling and wide-spread use of multicore processors
have dramatically increased the power consumption of main memory. It has been estimated …

A survey of techniques for improving error-resilience of DRAM

S Mittal, MS Inukonda - Journal of Systems Architecture, 2018 - Elsevier
Aggressive process scaling and increasing demands of performance/cost efficiency have
exacerbated the incidences and impact of errors in DRAM systems. Due to this …

Design and optimization of low voltage high performance dual threshold CMOS circuits

L Wei, Z Chen, M Johnson, K Roy, V De - Proceedings of the 35th annual …, 1998 - dl.acm.org
Reduction in leakage power has become an important concern in low voltage, low power
and high performance applications. In this paper, we use dual threshold technique to reduce …

Synergy: Rethinking secure-memory design for error-correcting memories

G Saileshwar, PJ Nair, P Ramrakhyani… - … Symposium on High …, 2018 - ieeexplore.ieee.org
Building trusted data-centers requires resilient memories which are protected from both
adversarial attacks and errors. Unfortunately, the state-of-the-art memory security solutions …