To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …

With the rapid developments in VLSI technology, the communication channels in networks-
on-chip (NoCs) can place many wires for sustaining high-performance requirements over …

Ensuring reliable data transmission in multicore System on Chip (SoC), which employs
Network on Chip (NoC), is a challenging task. This task is well addressed by Error …

Abstract Networks-on-chip (NoC) provide the communication infrastructure for high-speed
and large-scale computation that integrates several IP-cores on a single die. Faults on …

Aggressive scaling of CMOS process technology allows the fabrication of highly integrated
chips such as NoC-based MPSoCs. However, fault probability increases when devices' size …

Reliability of semiconductor devices requires testing of the chips for faults from multiple fault
models. When test generation is used for producing top off tests to detect faults from different …

As the technology is scaling down more number of processing elements are integrated on to
a single chip, namely system-on-chips (SoCs). Using traditional bus architecture in SoCs …

In the nano-scale era, to improve the system reliability the major challenge is to predict the
NoC component failures in runtime and propose an efficient technique. To predict the …

Real-time computing systems are designed to meet strict timing constraints and respond to
events or inputs within specific deadlines. These systems are commonly used in safety …

The communication in Network-on-Chips (NoCs) may be subject to errors. Error Correcting
Codes (ECCs) can be used to tolerate the transient faults in flits caused by Single Event …