GraphA: An efficient ReRAM-based architecture to accelerate large scale graph processing
SA Ghasemi, B Jahannia, H Farbeh - Journal of Systems Architecture, 2022 - Elsevier
Graph analytics is the basis for many modern applications, eg, machine learning and
streaming data problems. With an unprecedented increase in data size of many emerging …
streaming data problems. With an unprecedented increase in data size of many emerging …
Downshift: Tuning shift reduction with reliability for racetrack memories
Ultra-dense non-volatile racetrack memories (RTMs) have been investigated at various
levels in the memory hierarchy for improved performance and reduced energy consumption …
levels in the memory hierarchy for improved performance and reduced energy consumption …
Brain-inspired Cognition in Next-generation Racetrack Memories
Hyperdimensional computing (HDC) is an emerging computational framework inspired by
the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike …
the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike …
Sustainable AI processing at the edge
Edge computing is a popular paradigm for accelerating light-to medium-weight machine
learning algorithms initiated from mobile devices without requiring the long communication …
learning algorithms initiated from mobile devices without requiring the long communication …
Cinm (cinnamon): A compilation infrastructure for heterogeneous compute in-memory and compute near-memory paradigms
The rise of data-intensive applications exposed the limitations of conventional processor-
centric von-Neumann architectures that struggle to meet the off-chip memory bandwidth …
centric von-Neumann architectures that struggle to meet the off-chip memory bandwidth …
FPIRM: Floating-point Processing in Racetrack Memories
Convolutional neural networks (CNN) have become a ubiquitous algorithm with growing
applications in mobile and edge settings. We describe a compute-in-memory (CIM) …
applications in mobile and edge settings. We describe a compute-in-memory (CIM) …
XDWM: A 2D Domain Wall Memory
Domain-Wall Memory (DWM) structures typically bundle nanowires shifted together for
parallel access. Ironically, this organization does not allow the natural shifting of DWM to …
parallel access. Ironically, this organization does not allow the natural shifting of DWM to …
[PDF][PDF] Design and Code Optimization for Systems with Next-generation Racetrack Memories
AA Khan - 2022 - cfaed.tu-dresden.de
DESIGN AND CODE OPTIMIZATION FOR SYSTEMS WITH NEXT-GENERATION RACETRACK
MEMORIES Dissertation for the purpose of obtaining the d Page 1 DESIGN AND CODE …
MEMORIES Dissertation for the purpose of obtaining the d Page 1 DESIGN AND CODE …
Enabling Reliable Processing-in-Memory Augmented Storage for Spintronic Domain Wall Memory through Transverse Read
SSJL Ollivier - 2022 - search.proquest.com
In recent years, more and more proposals have been explored to replace conventional
SRAM, DRAM, and Flash with novel memories. Moreover, the performance gap between …
SRAM, DRAM, and Flash with novel memories. Moreover, the performance gap between …