FinFETs having strained channels, and methods of fabricating finFETs having strained channels

Q Liu, X Cai, R Xie, CC Yeh - US Patent 9,391,200, 2016 - Google Patents
Techniques and structures for controlling etch-back of a fin FET fin are described. One or
more layers may be deposited over the fin and etched. Etch-back of a planarization layer …

Semiconductor devices having a spacer on an isolation region

BJ Park, H Shin, CHO Hagju… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A semiconductor device including a fin active region pro truding from a
Substrate and an isolation region defining the fin active region, a gate pattern intersecting …

Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs

CY Huang, W Rachmady, MV Metz, G Dewey… - US Patent …, 2022 - Google Patents
A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the
buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor …

Fin field effect transistor including self-aligned raised active regions

A Basu, GM Cohen, A Majumdar - US Patent 9,196,711, 2015 - Google Patents
Fin mask structures are formed over a semiconductor material portion on a crystalline
insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask …

Structure having group III-V, Ge and SiGe Fins on insulator

S Mochizuki, A Reznicek - US Patent 9,761,609, 2017 - Google Patents
(57) ABSTRACT A method provides a first substrate supporting an insulator layer having
trenches formed therein; filling the trenches using an epitaxial growth process with at least …

Fin-type field effect transistor structure and manufacturing method thereof

CH Tsai, Z Fang, SK Jangjian, KW Chen… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A fin-type field effect transistor comprising a substrate, at least one gate
structure, first spacers, second spacers and source and drain regions is described. The …

Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending

YU De-Wei, CH Chen, CA Chang, PJ Liang - US Patent 10,504,747, 2019 - Google Patents
(57) ABSTRACT A method includes depositing a silicon layer, which includes first portions
over a plurality of strips, and second portions filled into trenches between the plurality of …

Forming a fin using double trench epitaxy

VS Basker, P Hashemi, S Mochizuki… - US Patent …, 2017 - Google Patents
The present invention relates generally to semiconductor devices and more particularly, to a
structure and method of forming a fin using double trench epitaxy. The fin may be composed …

III-V semiconductor CMOS FinFET device

H Jagannathan, A Reznicek, DK Sadana… - US Patent …, 2016 - Google Patents
(57) ABSTRACT A method for forming a semiconductor device comprises forming an
insulator layer on a semiconductor Substrate, removing portions of the insulator layer to form …

Forming a fin using double trench epitaxy

VS Basker, P Hashemi, S Mochizuki… - US Patent …, 2018 - Google Patents
The present invention relates generally to semiconductor devices and more particularly, to a
structure and method of forming a fin using double trench epitaxy. The fin may be composed …