To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …

With the increase in the network size, the conventional network-on-chip (NoC) imposes high
latency due to the lack of shorter paths between far nodes resulting in performance …

With the continuous growth in technology, the role of nano-electronic systems is rapidly
expanding in every facet of modern life. Subsequently, the demand of high performance …

This paper presents a fast and low cost on-line scheme named Charka that analyzes short
faults in channels of octagon NoCs. Experimental results demonstrate that the proposed …

The constant reduction in the components size in integrated circuits and the increase of the
operating frequency make Systems-on-Chip (SoCs) more vulnerable to noise and other …

The on-chip network, commonly known as network-on-chip (NoC) on a die as an alternate
prevalent interconnection infrastructure, has been continuously occupying the space of …

Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to
network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes …

The network-on-chip (NoC) paradigm has emerged as a high-performance communication
architecture for integrating many IP cores on a single die. The benefit of performances …

With the ever shrinking dimension of a chip on a die, it is evident that the channels of on-chip
networks (NoCs) are often exposed to logic level manufacturing faults such as stuck-at …

This paper proposes a cluster-based, distributed scheme for on-line testing of short faults in
NoC interconnects. Proposed scheme detects both intra-and inter-interconnect short faults …