A survey of timing verification techniques for multi-core real-time systems

C Maiza, H Rihani, JM Rivas, J Goossens… - ACM Computing …, 2019 - dl.acm.org
This survey provides an overview of the scientific literature on timing verification techniques
for multi-core real-time systems. It reviews the key results in the field from its origins around …

GPU devices for safety-critical systems: A survey

J Perez-Cerrolaza, J Abella, L Kosmidis… - ACM Computing …, 2022 - dl.acm.org
Graphics Processing Unit (GPU) devices and their associated software programming
languages and frameworks can deliver the computing performance required to facilitate the …

Multi-core interference-sensitive WCET analysis leveraging runtime resource capacity enforcement

J Nowotsch, M Paulitsch, D Bühler… - 2014 26th Euromicro …, 2014 - ieeexplore.ieee.org
The performance and power efficiency of multi-core processors are attractive features for
safety-critical applications, as in avionics. But increased integration and average-case …

Mixed criticality systems—a history of misconceptions?

R Ernst, M Di Natale - IEEE Design & Test, 2016 - ieeexplore.ieee.org
Mixed criticality systems have recently received much attention both in research and in
industrial design practice. However, industrial practice and much of the research community …

Outstanding paper award: Making shared caches more predictable on multicore platforms

BC Ward, JL Herman, CJ Kenna… - 2013 25th Euromicro …, 2013 - ieeexplore.ieee.org
In safety-critical cyber-physical systems, the usage of multicore platforms has been
hampered by problems due to interactions across cores through shared hardware. The …

Memory access control in multiprocessor for real-time systems with mixed criticality

H Yun, G Yao, R Pellizzoni… - 2012 24th Euromicro …, 2012 - ieeexplore.ieee.org
Shared resource access interference, particularly memory and system bus, is a big
challenge in designing predictable real-time systems because its worst case behavior can …

A coordinated approach for practical OS-level cache management in multi-core real-time systems

H Kim, A Kandhalu, R Rajkumar - 2013 25th Euromicro …, 2013 - ieeexplore.ieee.org
Many modern multi-core processors sport a large shared cache with the primary goal of
enhancing the statistic performance of computing workloads. However, due to resulting …

A closer look at intel resource director technology (rdt)

P Sohal, M Bechtel, R Mancuso, H Yun… - Proceedings of the 30th …, 2022 - dl.acm.org
Unarbitrated contention over shared resources at different levels of the memory hierarchy
represents a major source of temporal interference. Hardware manufacturers are …

Contention-free execution of automotive applications on a clustered many-core platform

M Becker, D Dasari, B Nicolic… - 2016 28th Euromicro …, 2016 - ieeexplore.ieee.org
Next generations of compute-intensive real-time applications in automotive systems will
require more powerful computing platforms. One promising power-efficient solution for such …

Predictable flight management system implementation on a multicore processor

G Durrieu, M Faugère, S Girbal, DG Pérez… - Embedded Real Time …, 2014 - hal.science
This paper presents an approach for hosting a representative avionic function on a
distributed-memory mul-ticore COTS architecture. This approach was developed in …