A transformation-based approach to hardware design using higher-order functions
R Wester - 2015 - research.utwente.nl
The amount of resources available on reconfigurable logic devices like FPGAs has seen a
tremendous growth over the last thirty years. During this period, the amount of …
tremendous growth over the last thirty years. During this period, the amount of …
The Reduceron reconfigured and re-evaluated
M Naylor, C Runciman - Journal of Functional Programming, 2012 - cambridge.org
A new version of a special-purpose processor for running lazy functional programs is
presented. This processor–the Reduceron–exploits parallel memories and dynamic …
presented. This processor–the Reduceron–exploits parallel memories and dynamic …
Structured Combinators for Efficient Graph Reduction
C Accetti, R Ying, P Liu - IEEE Computer Architecture Letters, 2022 - ieeexplore.ieee.org
Combinators have a long history in mathematics, logic and computer science, as simple
primitive symbols with which complex relationships can be described. In practice, this …
primitive symbols with which complex relationships can be described. In practice, this …
Heron: Modern Hardware Graph Reduction
C Ramsay, R Stewart - The 35th Symposium on Implementation and …, 2023 - dl.acm.org
FPGAs have enjoyed exponential growth of on-chip hardware resources—reason to
reinvestigate hardware implementations of functional languages. This paper presents …
reinvestigate hardware implementations of functional languages. This paper presents …
Architectural Support for Functional Programming
C Accetti, P Liu - 2022 IFIP/IEEE 30th International Conference …, 2022 - ieeexplore.ieee.org
The architecture of a computer determines what programs are allowed to do and what the
microarchitecture should implement. As security and safety become critical needs for an …
microarchitecture should implement. As security and safety become critical needs for an …
ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs
R Coelho, F Tanus, Á Moreira… - 2020 IEEE Computer …, 2020 - ieeexplore.ieee.org
Typical reconfigurable accelerators are either limited to instruction-level parallelism or
require developers to manage parallelism in the source code manually. Pure functional …
require developers to manage parallelism in the source code manually. Pure functional …
Programming models for many-core architectures: a co-design approach
JH Rutgers - 2014 - research.utwente.nl
Common many-core processors contain tens of cores and distributed memory. Compared to
a multicore system, which only has a few tightly coupled cores sharing a single bus and …
a multicore system, which only has a few tightly coupled cores sharing a single bus and …
Programming a Multicore Architecture without Coherency and Atomic Operations
It is hard to reason about the state of a multicore system-on-chip, because operations on
memory need multiple cycles to complete, since cores communicate via an interconnect like …
memory need multiple cycles to complete, since cores communicate via an interconnect like …
Adaptive architecture-transparent policy control in a distributed graph reducer
E Belikov - 2019 - ros.hw.ac.uk
The end of the frequency scaling era occured around 2005 as the clock frequency has
stalled for commodity architectures. Thus performance improvements that could in the past …
stalled for commodity architectures. Thus performance improvements that could in the past …
Ο Νοηματικός Μετασχηματισμός ως Τεχνική Υλοποίησης Συναρτησιακών Γλωσσών Προγραμματισμού
ΓΑ Φουρτούνης - 2014 - dspace.lib.ntua.gr
Οι γλώσσες προγραμματισμού με μη αυστηρή σημασιολογία χρησιμοποιούνται για τη
συγγραφή προγραμμάτων στα οποία μια έκφραση μπορεί να αντιστοιχίζεται σε ένα όνομα …
συγγραφή προγραμμάτων στα οποία μια έκφραση μπορεί να αντιστοιχίζεται σε ένα όνομα …