A survey on cache tuning from a power/energy perspective
W Zang, A Gordon-Ross - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Low power and/or energy consumption is a requirement not only in embedded systems that
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …
Low power processor architectures and contemporary techniques for power optimization–a review
MY Qadri, HS Gujarathi… - Journal of …, 2009 - repository.essex.ac.uk
The technological evolution has increased the number of transistors for a given die area
significantly and increased the switching speed from few MHz to GHz range. Such inversely …
significantly and increased the switching speed from few MHz to GHz range. Such inversely …
Filter data cache: An energy-efficient small L0 data cache architecture driven bymiss cost reduction
J Lee, S Kim - IEEE Transactions on Computers, 2014 - ieeexplore.ieee.org
On-chip cache memories play an important role in resource-constrained embedded systems
by filtering out most off-chip memory accesses. Because cache latency and energy …
by filtering out most off-chip memory accesses. Because cache latency and energy …
Non-uniform power access in large caches with low-swing wires
AN Udipi, N Muralimanohar… - … Conference on High …, 2009 - ieeexplore.ieee.org
Modern processors dedicate more than half their chip area to large L2 and L3 caches and
these caches contribute significantly to the total processor power. A large cache is typically …
these caches contribute significantly to the total processor power. A large cache is typically …
Instruction cache energy saving through compiler way-placement
Fetching instructions from a set-associative cache in an embedded processor can consume
a large amount of energy due to the tag checks performed. Recent proposals to address this …
a large amount of energy due to the tag checks performed. Recent proposals to address this …
Performance advantage of reconfigurable cache design on multicore processor systems
J Tao, M Kunze, F Nowak, R Buchty, W Karl - International Journal of …, 2008 - Springer
With the trends of microprocessor design towards multicore, cache performance becomes
more important because an off-chip access would be increasingly expensive due to the …
more important because an off-chip access would be increasingly expensive due to the …
A cache tuning heuristic for multicore architectures
M Rawlins, A Gordon-Ross - IEEE transactions on computers, 2013 - ieeexplore.ieee.org
Since multicore architectures are becoming more popular, recent multicore optimizations
focus on energy consumption. In this paper, we focus on reducing the energy consumption …
focus on energy consumption. In this paper, we focus on reducing the energy consumption …
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache
K Kang, G De Micheli, S Lee… - … Symposium on Quality …, 2014 - ieeexplore.ieee.org
The advent of 3-D fabrication technology makes it possible to stack a large amount of last-
level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus …
level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus …
Energy efficient i-cache using multiple line buffers with prediction
Modern microprocessors dedicate a large portion of the chip area to the cache. Decreasing
the energy consumption of the microprocessor, which is a very important design goal …
the energy consumption of the microprocessor, which is a very important design goal …
Energy management techniques for SOC design
One of the biggest problems in complicated and high-performance SoC design is
management of energy and/or power consumption. In this chapter, we present energy …
management of energy and/or power consumption. In this chapter, we present energy …