Relaxing non-volatility for fast and energy-efficient STT-RAM caches
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that
is a potential universal memory that could replace SRAM in processor caches. This paper …
is a potential universal memory that could replace SRAM in processor caches. This paper …
Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design
MK Qureshi, GH Loh - 2012 45th Annual IEEE/ACM …, 2012 - ieeexplore.ieee.org
This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior
research, including the recent work from Loh and Hill, have organized DRAM caches similar …
research, including the recent work from Loh and Hill, have organized DRAM caches similar …
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
MR Meswani, S Blagodurov, D Roberts… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Die-stacked DRAM is a technology that will soon be integrated in high-performance
systems. Recent studies have focused on hardware caching techniques to make use of the …
systems. Recent studies have focused on hardware caching techniques to make use of the …
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
Die-stacking technology enables multiple layers of DRAM to be integrated with multicore
processors. A promising use of stacked DRAM is as a cache, since its capacity is insufficient …
processors. A promising use of stacked DRAM is as a cache, since its capacity is insufficient …
Die-stacked dram caches for servers: Hit ratio, latency, or bandwidth? have it all with footprint cache
Recent research advocates using large die-stacked DRAM caches to break the memory
bandwidth wall. Existing DRAM cache designs fall into one of two categories---block-based …
bandwidth wall. Existing DRAM cache designs fall into one of two categories---block-based …
Unison cache: A scalable and effective die-stacked DRAM cache
Recent research advocates large die-stacked DRAM caches in many core servers to break
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …
Cameo: A two-level memory organization with capacity of main memory and flexibility of hardware-managed cache
CC Chou, A Jaleel, MK Qureshi - 2014 47th Annual IEEE/ACM …, 2014 - ieeexplore.ieee.org
This paper analyzes the trade-offs in architecting stacked DRAM either as part of main
memory or as a hardware-managed cache. Using stacked DRAM as part of main memory …
memory or as a hardware-managed cache. Using stacked DRAM as part of main memory …
A survey of techniques for architecting DRAM caches
Recent trends of increasing core-count and memory/bandwidth-wall have led to major
overhauls in chip architecture. In face of increasing cache capacity demands, researchers …
overhauls in chip architecture. In face of increasing cache capacity demands, researchers …
Heteroos: Os design for heterogeneous memory management in datacenter
S Kannan, A Gavrilovska, V Gupta… - Proceedings of the 44th …, 2017 - dl.acm.org
Heterogeneous memory management combined with server virtualization in datacenters is
expected to increase the software and OS management complexity. State-of-the-art …
expected to increase the software and OS management complexity. State-of-the-art …
Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management
Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories
such as phase-change memory (PCM) can provide much larger storage capacity than …
such as phase-change memory (PCM) can provide much larger storage capacity than …