FIMSIM: A fault injection infrastructure for microarchitectural simulators
Fault injection is a widely used approach for experiment-based dependability evaluation.
Injecting faults to microarchitectural simulators is particularly appealing for researchers …
Injecting faults to microarchitectural simulators is particularly appealing for researchers …
FaulTM: error detection and recovery using hardware transactional memory
Reliability is an essential concern for processor designers due to increasing transient and
permanent fault rates. Executing instruction streams redundantly in chip multi processors …
permanent fault rates. Executing instruction streams redundantly in chip multi processors …
Combining error detection and transactional memory for energy-efficient computing below safe operation margins
G Yalcin, A Sobe, D Harmanci… - … , and Network-Based …, 2014 - ieeexplore.ieee.org
The power envelope has become a major issue for the design of computer systems. One
way of reducing energy consumption is to downscale the voltage of microprocessors …
way of reducing energy consumption is to downscale the voltage of microprocessors …
Revisiting symptom-based fault tolerant techniques against soft errors
Aggressive technology scaling and near-threshold computing have made soft error reliability
one of the leading design considerations in modern embedded microprocessors. Although …
one of the leading design considerations in modern embedded microprocessors. Although …
Applying Hardware Transactional Memory for {Concurrency-Bug} Failure Recovery in Production Runs
Concurrency bugs widely exist and severely threaten system availability. Techniques that
help recover from concurrency-bug failures during production runs are highly desired. This …
help recover from concurrency-bug failures during production runs are highly desired. This …
Transactional encoding for tolerating transient hardware errors
JT Wamhoff, M Schwalbe, R Faqeh, C Fetzer… - Stabilization, Safety, and …, 2013 - Springer
The decreasing feature size of integrated circuits leads to less reliable hardware with higher
likelihood for errors. Without adding additional failure detection and masking mechanisms …
likelihood for errors. Without adding additional failure detection and masking mechanisms …
[PDF][PDF] Leveraging transactional memory for energyefficient computing below safe operation margins
The power envelope has become a major issue for the design of computer systems. One
way of reducing energy consumption is to downscale the voltage of microprocessors …
way of reducing energy consumption is to downscale the voltage of microprocessors …
Detection of Silent Data Corruption in fault-tolerant distributed systems on board spacecraft
M Fayyaz, T Vladimirova - 2014 NASA/ESA Conference on …, 2014 - ieeexplore.ieee.org
In this paper a novel distributed architecture for system level Fault Detection, Isolation and
Recovery (FDIR) aimed at spacecraft applications is presented. The architecture …
Recovery (FDIR) aimed at spacecraft applications is presented. The architecture …
Task Oriented Fault-Tolerant Distributed Computing for Use on Board Spacecraft
M Fayyaz - 2016 - figshare.le.ac.uk
Current and future space missions demand highly reliable, High Performance Embedded
Computing (HPEC). The review of the literature has shown that no single solution could …
Computing (HPEC). The review of the literature has shown that no single solution could …
Applying transactional memory for concurrency-bug failure recovery in production runs
Concurrency bugs widely exist and severely threaten system availability. Techniques that
help recover from concurrency-bug failures during production runs are highly desired. This …
help recover from concurrency-bug failures during production runs are highly desired. This …