On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers
Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1
and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips …
and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips …
An energy efficient and reliable multipath transmission strategy for mobile wireless sensor networks
C Sun, Z Wang, D Lu, L Cao, Y Yue… - Computational …, 2022 - Wiley Online Library
Multipath data transmission is a key problem that needs to be solved urgently in wireless
sensor networks. In this paper, sensor node failure, link failure, energy exhaustion, and …
sensor networks. In this paper, sensor node failure, link failure, energy exhaustion, and …
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application
Multiple cell upset (MCU) caused by cosmic radiation is a serious issue related to the
reliability of static random access memories (SRAMs) in space application. Due to radiation …
reliability of static random access memories (SRAMs) in space application. Due to radiation …
Lightweight Microcontroller with Parallelized ECC-Based Code Memory Protection Unit for Robust Instruction Execution in Smart Sensors
Embedded systems typically operate in harsh environments, such as where there is external
shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these …
shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these …
FPGA based low area multi-bit adjacent error correcting codec for SRAM application
Mostly random and adjacent error correcting codes are used to protect stored data in
SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an …
SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an …
A comprehensive framework for analysis of time-dependent performance-reliability degradation of SRAM cache memory
This article describes a comprehensive framework for analysis of time-dependent
performance-reliability degradation of an SRAM cache, considering cache configurations …
performance-reliability degradation of an SRAM cache, considering cache configurations …
Compact and high-speed Hsiao-based SEC-DED codec for cache memory
J Samanta, A Kewat - Journal of Circuits, Systems and Computers, 2022 - World Scientific
Recently, there have been continuous rising interests of multi-bit error correction codes
(ECCs) for protecting memory cells from soft errors which may also enhance the reliability of …
(ECCs) for protecting memory cells from soft errors which may also enhance the reliability of …
FPGA and ASIC-Based Design of Fast and Low Power SEC-DAEC and SEC-DAEC-TAEC Codecs
Soft errors greatly affect the reliability of static random access memories, which mainly occur
due to cosmic radiations. These soft errors may lead to multiple cell upsets (MCUs). To …
due to cosmic radiations. These soft errors may lead to multiple cell upsets (MCUs). To …
[PDF][PDF] Algorithm and data encoding/decoding devices based on two-dimensional modular correction codes.
In the paper, an error detection and correction algorithm was developed on the basis of
modular correcting codes and a two-dimensional scheme. The developed algorithm …
modular correcting codes and a two-dimensional scheme. The developed algorithm …
Design of power efficient SEC orthogonal Latin Square (OLS) codes
Single event upset type of soft error caused by the ionizing radiation is a key constraint for
reliable memory design. To correct soft errors in memories, single error correction (SEC) …
reliable memory design. To correct soft errors in memories, single error correction (SEC) …