A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …

We present benchtop and in vivo experimental results from an integrated circuit designed for
wireless implantable neural recording applications. The chip, which was fabricated in a …

This paper presents class-D CMOS oscillators capable of an excellent phase noise
performance from a very low power supply voltage. Starting from the recognition of the time …

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital
converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to …

Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low
supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered …

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is
achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital …

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled
oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All …

This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

An exponentially scaling C-2C switched-capacitor (SC) ladder is proposed for millimeter-
wave digitally controlled oscillators (DCOs) to achieve high-frequency resolution with small …

This paper presents a 401-428-MHz BFSK/QPSK transmitter (TX) with two types of fractional-
injection-locking techniques for multichannel transmission capabilities. A ΔΣbased injection …