[图书][B] Hard real-time computing systems

GC Buttazzo, G Buttanzo - 1997 - Springer
Real-time computing plays a crucial role in our society since an increasing number of
complex systems rely, in part or completely, on computer control. Examples of applications …

A holistic memory contention analysis for parallel real-time tasks under partitioned scheduling

D Casini, A Biondi, G Nelissen… - 2020 IEEE Real-Time …, 2020 - ieeexplore.ieee.org
When adopting multi-core systems for safety-critical applications, certification requirements
mandate bounding the delays incurred in accessing shared resources. This is the case of …

Leveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC

A Serrano Cases, JM Reina… - … Conference on Real …, 2021 - upcommons.upc.edu
The interference co-running tasks generate on each other's timing behavior continues to be
one of the main challenges to be addressed before Multi-Processor System-on-Chip …

Axi hyperconnect: A predictable, hypervisor-level interconnect for hardware accelerators in fpga soc

F Restuccia, A Biondi, M Marinoni… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
FPGA-based system-on-chips (SoC) are powerful computing platforms to implement mixed-
criticality systems that require both multiprocessing and hardware acceleration …

AKER: A design and verification framework for safe and secure soc access control

F Restuccia, A Meza, R Kastner - 2021 IEEE/ACM International …, 2021 - ieeexplore.ieee.org
Modern systems on a chip (SoCs) utilize heterogeneous architectures where multiple IP
cores have concurrent access to on-chip shared resources. In security-critical applications …

Time-predictable acceleration of deep neural networks on fpga soc platforms

F Restuccia, A Biondi - 2021 IEEE Real-Time Systems …, 2021 - ieeexplore.ieee.org
This work focuses on the time-predictable execution of Deep Neural Networks (DNNs)
accelerated on FPGA System-on-Chips (SoCs). The modern DPU accelerator by Xilinx is …

Latency analysis of I/O virtualization techniques in hypervisor-based real-time systems

D Casini, A Biondi, G Cicero… - 2021 IEEE 27th Real …, 2021 - ieeexplore.ieee.org
Nowadays, hypervisors are the standard solution to integrate different domains into a shared
hardware platform, while providing safety, security, and predictability. To this end, a …

{OSMOSIS}: Enabling {Multi-Tenancy} in Datacenter {SmartNICs}

M Khalilov, M Chrapek, S Shen, A Vezzu… - 2024 USENIX Annual …, 2024 - usenix.org
Multi-tenancy is essential for unleashing SmartNIC's potential in datacenters. Our systematic
analysis in this work shows that existing on-path SmartNICs have resource multiplexing …

Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs

F Restuccia, M Pagani, A Biondi… - … Conference on Real …, 2020 - drops.dagstuhl.de
Abstract FPGA System-on-Chips (SoCs) are heterogeneous platforms that combine general-
purpose processors with a field-programmable gate array (FPGA) fabric. The FPGA fabric is …

Serving multi-DNN workloads on FPGAs: A coordinated architecture, scheduling, and mapping perspective

S Zeng, G Dai, N Zhang, X Yang… - IEEE Transactions …, 2022 - ieeexplore.ieee.org
Deep Neural Network (DNN) INFerence-as-a-Service (INFaaS) is the dominating workload
in current data centers, for which FPGAs become promising hardware platforms because of …