H-shaped VFET with increased current drivability

C Zhang, K Cheng, T Yamashita, X Miao… - US Patent …, 2019 - Google Patents
Techniques for increasing Weff VFET devices are provided. In one aspect, a method of
forming a fin structure includes: depositing a hardmask onto a substrate; depositing a …

Electrical modeling of lithographic imperfections

TB Chan, RS Ghaida, P Gupta - 2010 23rd International …, 2010 - ieeexplore.ieee.org
Lithographic wavelength of 193 nm has been used for past few generations of patterning
and is likely to remain in use for next few technology generations (at least till 28 nm …

Glomerulus extraction by optimizing the fitting curve

J Zhang, J Hu - 2008 International Symposium on …, 2008 - ieeexplore.ieee.org
Glomerulus extraction is an important step for automatic analysis of the kidney diseases in
the computer-aided diagnosis system. A method based on searching the best fitting curve is …

DFM is dead-Long live DFM

R Aitken, D Pietromonaco… - 2014 IEEE 32nd …, 2014 - ieeexplore.ieee.org
For many years, a key aspect of Design-for-Manufacturability (DFM) has been adjustment of
polygons in standard cell layout. Similarly, radically restricted design rules and …

Transistor layout optimization for leakage saving

M Ryu, Y Kang, Y Kim - 2013 International SoC Design …, 2013 - ieeexplore.ieee.org
In this paper, we investigate electrical effects of transistor layout shape (both in the channel
and diffusion) on the performance and leakage current. Through layout optimization …

Efficient characterization and suppression methodology of edge effects for leakage current reduction of sub-40nm DRAM device

SH Choi, YH Park, CH Park, SH Lee… - 2010 International …, 2010 - ieeexplore.ieee.org
With the process scaling, the leakage current reduction has been the primary design
concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography …

Intra-Gate Length Biasing for Leakage Optimization in 45 nm Technology Node

Y Kang, Y Kim - IEICE Transactions on Fundamentals of …, 2013 - search.ieice.org
Due to the increasing need for low-power circuits in mobile applications, numerous leakage
and performance optimization techniques are being used in modern ICs. In the present …

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC

G Chen, Y Zhang, Q Dong, MY Li… - IEICE Transactions on …, 2015 - search.ieice.org
As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits
is becoming a dominant contributor to power dissipation. This paper provides an efficient …

[PDF][PDF] Estudo do efeito do desalinhamento da máscara de porta sobre a corrente de dreno em MOSFETs com geometria de porta trapezoidal

DS Sabbadin - 2014 - repositorio.fei.edu.br
Este trabalho trata do estudo do efeito do desalinhamento da máscara de porta sobre as
características elétricas dos MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) …

Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device

SH Choi, YH Park, CH Park, SH Lee… - IEICE transactions on …, 2010 - search.ieice.org
With the process scaling, the leakage current reduction has been the primary design
concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography …