A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length
VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes
VB Sreenivasulu, V Narendar - AEU-International Journal of Electronics …, 2022 - Elsevier
Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET
In this paper, the effect of channel parameters like channel thickness (T Si) and channel
length (L g) on the analog/RF performance of high-K gate-stack based junctionless Trigate …
length (L g) on the analog/RF performance of high-K gate-stack based junctionless Trigate …
Performance evaluation of spacer dielectric engineered vertically stacked junctionless nanosheet FET for sub-5 nm technology node
This manuscript for the first time provides insights on the impact of different spacer materials
for the vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The …
for the vertically stacked Junctionless Nanosheet Field Effect Transistor (JL-NSFET). The …
Optimization of Device Dimensions of High-k Gate Dielectric Based DG-TFET for Improved Analog/RF Performance
The optimization of device dimensions along with high-k gate dielectric is investigated in this
work for improving RF/analog performance of double gate (DG) TFET device. Through …
work for improving RF/analog performance of double gate (DG) TFET device. Through …
Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective
This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance
This paper for the first time investigates the effect of temperature variation on analog/RF
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration
In this work, the investigation of high‐K gate‐stack‐based junctionless (JL) double‐gate
(DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the …
(DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the …
Gate oxide variability analysis of a novel 3 nm truncated fin–finfet for high circuitry performance
MP Kashyap, R Chaujar - Silicon, 2021 - Springer
In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm
Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this …
Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at this …
Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node
B Liu, J Zhu - Scientific Reports, 2023 - nature.com
The impact of spacer on the single event response of SOI FinFET at 14 nm technology node
is investigated. Based on the device TCAD model, well-calibrated by the experimental data …
is investigated. Based on the device TCAD model, well-calibrated by the experimental data …