Simulation comparison of hot-carrier degradation in nanowire, nanosheet and forksheet FETs
Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET
and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p-to …
and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p-to …
Improving the Tamper-Aware Odometer Concept by Enhancing Dynamic Stress Operation
J Diaz-Fortuny, D Sangani… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
On-chip degradation monitors have recently gained significant relevance because they can
provide real-time estimations of IC reliability by exploiting the fundamental physics of BTI …
provide real-time estimations of IC reliability by exploiting the fundamental physics of BTI …
Towards complete recovery of circuit degradation by annealing with on-chip heaters
J Diaz-Fortuny, P Saraza-Canflanca… - IEEE Electron …, 2022 - ieeexplore.ieee.org
This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a
versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip …
versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip …
Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range
We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a
wide range of gate and drain voltages (V gs and V ds, respectively). Special attention is paid …
wide range of gate and drain voltages (V gs and V ds, respectively). Special attention is paid …
Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations
M Vandemaele, B Kaczer, E Bury… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
We report TCAD simulation studies on nanowire (NW), nanosheet (NS) and forksheet (FS)
FET hot-carrier relia-bility. The simulations entail i) solving the Boltzmann transport equation …
FET hot-carrier relia-bility. The simulations entail i) solving the Boltzmann transport equation …
Modeling of repeated FET hot-carrier stress and anneal cycles using Si–H bond dissociation/passivation energy distributions
We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal
cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS …
cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS …
Demonstration of Chip Overclock Detection by Employing Tamper-Aware Odometer Technology
J Diaz-Fortuny, P Saraza-Canflanca… - 2024 IEEE …, 2024 - ieeexplore.ieee.org
Integrated circuits (IC) are the heart of all electronic systems in critical sectors like
automotive, aerospace, or healthcare, in key infrastructures like telecommunications …
automotive, aerospace, or healthcare, in key infrastructures like telecommunications …
Effectiveness of Repairing Hot Carrier Degradation in Si p-FinFETs Using Gate Induced Drain Leakage
H Chang, Q Liu, H Yang, L Zhou, Z Ji… - IEEE Electron …, 2023 - ieeexplore.ieee.org
In this study, the gate induced drain leakage (GIDL) of Si p-FinFET and its recovery effect on
hot carrier degradation (HCD) were experimentally studied to further its physical …
hot carrier degradation (HCD) were experimentally studied to further its physical …
The impact of self-heating and its implications on hot-carrier degradation–A modeling study
A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to
be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with …
be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with …
Improved self-curing effect in a MOSFET with gate biasing
GB Lee, JW Jung, CK Kim, T Bang… - IEEE Electron …, 2021 - ieeexplore.ieee.org
Stress-induced damage in a MOSFET can be cured by Joule heating, which can be
produced by an intentional forward junction current (). This curing effect can be further …
produced by an intentional forward junction current (). This curing effect can be further …