KiloCore: A 32-nm 1000-processor computational array

B Bohnenstiehl, A Stillmaker… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
A processor array containing 1000 independent processors and 12 memory modules was
fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable …

Evaluation of low power consumption network on chip routing architecture

TS Arulananth, M Baskar, US SM, R Thiagarajan… - Microprocessors and …, 2021 - Elsevier
Abstract Network on Chip (NoC) is growing technology whereby multiprocessor state
interconnect patterns are formed. NoC technology is adapted to support a variety of …

A 5.8 pj/op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array

B Bohnenstiehl, A Stillmaker, J Pimentel… - … IEEE Symposium on …, 2016 - ieeexplore.ieee.org
1000 programmable processors and 12 independent memory modules capable of
simultaneously servicing both data and instruction requests are integrated onto a 32nm PD …

An efficient low latency router architecture for mesh-based NoC

A Sai Kumar, TVK Hanumantha Rao - Advances in Communications …, 2021 - Springer
NoC is a growing technology where interconnected patterns are developed in the state of
multiprocessors. Due to the complicated routing links, many issues prevail regarding traffic …

An Efficient Low-Power VIP-based VC Router Architecture for Mesh-based NoC

BNK Reddy, AS Kumar - 2022 IEEE 19th India Council …, 2022 - ieeexplore.ieee.org
Network-on-Chip is an emerging paradigm in the domain of multi-processors wherein
interconnected patterns were constructed. Numerous problems with traffic congestion …

MRBS: An area-efficient multicast router for network-on-chip using buffer sharing

MC Yang, YS Lee, TH Han - IEEE Access, 2021 - ieeexplore.ieee.org
Network-on-chip (NoC) has become the mainstream fabric architecture for chip
multiprocessor (CMP) design. Owing to the market-driven advancement of modern …

An efficient network-on-chip router for dataflow architecture

XW Shen, XC Ye, X Tan, D Wang, L Zhang… - Journal of Computer …, 2017 - Springer
Dataflow architecture has shown its advantages in many high-performance computing
cases. In dataflow computing, a large amount of data are frequently transferred among …

Enhancing network-on-chip performance by reusing trace buffers

N Jindal, S Gupta, DP Ravipati… - IEEE transactions on …, 2019 - ieeexplore.ieee.org
Ensuring the functional correctness of networks-on-chip (NoCs) can be particularly
challenging, and communication-centric debug methodologies have been widely used by …

SB-Router: A swapped buffer activated low latency network-on-chip router

M Katta, TK Ramesh, J Plosila - IEEE Access, 2021 - ieeexplore.ieee.org
Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its
performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally …

Improving power and performance of on-chip network through virtual channel sharing and power gating

D Xu, Y Ouyang, W Zhou, H Liang - Integration, 2023 - Elsevier
Abstract Networks-on-Chip (NoCs) are becoming the communication backbone in multicore
chips. The router buffer holds a critical significance for the communication performance of …