Automatic generation of efficient accelerators for reconfigurable hardware
Acceleration in the form of customized datapaths offer large performance and energy
improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are …
improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are …
Chordmap: Automated mapping of streaming applications onto cgra
Streaming applications, consisting of several communicating kernels, are ubiquitous in the
embedded computing systems. The synchronous data flow (SDF) is commonly used to …
embedded computing systems. The synchronous data flow (SDF) is commonly used to …
Automated accelerator generation and optimization with composable, parallel and pipeline architecture
CPU-FPGA heterogeneous architectures feature flexible acceleration of many workloads to
advance computational capabilities and energy efficiency in today's datacenters. This …
advance computational capabilities and energy efficiency in today's datacenters. This …
The Feniks FPGA operating system for cloud computing
Driven by explosive demand on computing power and slowdown of Moore's law, cloud
providers have started to deploy FPGAs into datacenters for workload offloading and …
providers have started to deploy FPGAs into datacenters for workload offloading and …
Bandwidth optimization through on-chip memory restructuring for HLS
High-level synthesis (HLS) is getting increasing attention from both academia and industry
for high-quality and high-productivity designs. However, when inferring primitive-type arrays …
for high-quality and high-productivity designs. However, when inferring primitive-type arrays …
The TaPaSCo Open-Source Toolflow: for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems
The integration of FPGA-based accelerators into a complete heterogeneous system is a
challenging task faced by many researchers and engineers, especially now that FPGAs …
challenging task faced by many researchers and engineers, especially now that FPGAs …
Best-effort FPGA programming: A few steps can go a long way
FPGA-based heterogeneous architectures provide programmers with the ability to customize
their hardware accelerators for flexible acceleration of many workloads. Nonetheless, such …
their hardware accelerators for flexible acceleration of many workloads. Nonetheless, such …
Customizable computing—from single chip to datacenters
Since its establishment in 2009, the Center for Domain-Specific Computing (CDSC) has
focused on customizable computing. We believe that future computing systems will be …
focused on customizable computing. We believe that future computing systems will be …
Composable, parameterizable templates for high-level synthesis
High-level synthesis tools aim to make FPGA programming easier by raising the level of
programming abstraction. Yet in order to get an efficient hardware design from HLS tools …
programming abstraction. Yet in order to get an efficient hardware design from HLS tools …
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers
P Fezzardi, F Ferrandi - 2016 26th International Conference on …, 2016 - ieeexplore.ieee.org
Modern High-Level Synthesis (HLS) compilers aggressively optimize memory architectures.
Bugs involving memory accesses are hard to detect, especially if they are inserted in the …
Bugs involving memory accesses are hard to detect, especially if they are inserted in the …