A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

A continuous-rate digital clock and data recovery (CDR) with automatic frequency
acquisition is presented. The proposed automatic frequency acquisition scheme …

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops
(FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously …

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital
frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the …

Although multiplying delay-locked loops allow clock frequency multiplication with very low
phase noise and jitter, their application has been so far limited to integer-N multiplication …

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-
locked loop provides a high-frequency clock to multiple independent open loop ΔΣ fractional …

Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs),
which contain microprocessors, I/O interfaces, memories, power management, and …

A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented.
The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs …

This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band
Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse …