Recent Advances in Gate Dielectrics for Enhanced Leakage Current Management and Device Performance

Y Jeong, J Cho, DP Pham, J Yi - Transactions on Electrical and Electronic …, 2024 - Springer
Gate oxide in metal oxide semiconductor field effect transistor (MOSFET) or gate dielectric
layer in thin film transistor (TFT) plays an important role in the inhibition of leakage current …

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

E Živanović, S Veljković, N Mitrović, I Jovanović… - Micromachines, 2024 - mdpi.com
This study aimed to comprehensively understand the performance and degradation of both
p-and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature …

Research on equivalent modeling and model testing verification methods for material mechanics parameters of TXV structure

T Gu, N Liu, Z Feng, X Sun, X Meng - Microelectronics Reliability, 2024 - Elsevier
Aiming at the problems of multi-scale mesh division and low computational efficiency
encountered during TXV (through X via) structural simulation, an equivalent modeling …

Low-power Rapid Planar Superconducting Logic Devices

N Gusarov, R Mandal, I Salameh, I Holzman… - arXiv preprint arXiv …, 2024 - arxiv.org
The rapid-pace growing demand for high-performance computation and big-data
manipulation entails substantial increase in global power consumption, and challenging …

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

U Sharma, M Jhamb - Engineering Research Express, 2024 - iopscience.iop.org
Fundamental to digital signal processing applications such as the Arithmetic Logic Unit
(ALU), logic gates serve as the foundational components. This paper presents NOR and …

Parameters optimization to minimize the power dissipation of FiNFET 7 nm

L Abdelaziz, B Khaled… - 2024 16th International …, 2024 - ieeexplore.ieee.org
FinFET device represents an alternative solution to overcome the Short Channel Effect
(SCE). In this paper, a layout based FinFET design approach has been presented at 7 nm …