Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

PV Praveen Sundar, D Ranjith, T Karthikeyan… - International Journal of …, 2020 - Springer
In this paper, we propose a low complex architectural design for hearing aid applications. In
this, we recast the hearing aid using distributed arithmetic (DA), which enables the …

[HTML][HTML] Area and delay efficient RNS-based FIR filter design using fast multipliers

M Balaji, N Padmaja - Measurement: Sensors, 2024 - Elsevier
In today's digital age, speed, and area are the primary design concerns. Increasing the rate
at which multiplication and addition are performed has always been a need for developing …

High speed low area OBC DA based decimation filter for hearing aids application

G NagaJyothi, S Sridevi - International Journal of Speech Technology, 2020 - Springer
This brief presents a decimation filter for hearing aid application using distributed arithmetic
(DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA …

[PDF][PDF] Design and implementation of DA FIR filter for bio-inspired computing architecture

BUV Prashanth, MR Ahmed… - International Journal of …, 2021 - academia.edu
This paper elucidates the system construct of DA-FIR filter optimized for design of distributed
arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly …

Design of FIR filter with Fast Adders and Fast Multipliers using RNS Algorithm

M Balaji, N Padmaja, P Gitanjali… - 2023 4th …, 2023 - ieeexplore.ieee.org
The primary driving force behind the creation of this work was to provide the design and
implementation of a 4-tap, 8-tap, 16-tap, 32-tap, and 64-tap RNS (Residue Number System) …

[PDF][PDF] High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design

M Balaji, N Padmaja - WSEAS Transactions on Systems and Control, 2022 - wseas.com
Digital FIR Filters plays a major role in many signal processing applications. Generally,
these filters are designed with multipliers and adders to find the filter output. This paper …

Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

SSH Krishnan, K Vidhya - Expert Systems with Applications, 2024 - Elsevier
In this manuscript, a High Throughput and Low Latency DA-FIR filter design is integrated
with Approximate Karatsuba Multiplier (AKM) and Variable Latency Carry Skip Adder …

Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal …

RD Kulkarni, MA Majid - Integration, 2024 - Elsevier
An energy-efficient architecture of high-performance FIR adaptive filter design using
approximate distributed arithmetic (DA), which is integrated with canonic signed digit-based …

Low Area High-speed Hardware Implementation of Fast FIR Algorithm for Intelligent Signal Processing application in Complex Industrial Systems

P Pondreti, K Babulu - Journal of Signal Processing Systems, 2023 - Springer
Abstract Finite Impulse Response (FIR) filters are widely used in biomedical, communication
and audio signal processing applications due to their various advantages such as …

Distributed arithmetic RNS-based FIR filter design using pipelining and retiming methods for high-speed DSP systems

M Balaji, N Padmaja - 2022 - researchsquare.com
This work presents a way to increase the throughput and energy efficiency of finite impulse
response (FIR) filters through the efficient application of retiming and two-level pipelining. It …