A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches

S Mittal, JS Vetter, D Li - IEEE Transactions on Parallel and …, 2014 - ieeexplore.ieee.org
Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Z Wang, DA Jiménez, C Xu, G Sun… - 2014 IEEE 20th …, 2014 - ieeexplore.ieee.org
Emerging Non-Volatile Memories (NVM) such as Spin-Torque Transfer RAM (STT-RAM)
and Resistive RAM (RRAM) have been explored as potential alternatives for traditional …

[HTML][HTML] All-in-memory brain-inspired computing using fefet synapses

S Thomann, HLG Nguyen, PR Genssler… - Frontiers in …, 2022 - frontiersin.org
The separation of computing units and memory in the computer architecture mandates
energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is …

Performance analysis of the memory management unit under scale-out workloads

V Karakostas, OS Unsal, M Nemirovsky… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
Much attention has been given to the efficient execution of the scale-out applications that
dominate in datacenter computing. However, the effects of the hardware support in the …

A survey of non-volatile main memory technologies: State-of-the-arts, practices, and future directions

HK Liu, D Chen, H Jin, XF Liao, B He, K Hu… - Journal of Computer …, 2021 - Springer
Abstract Non-Volatile Main Memories (NVMMs) have recently emerged as a promising
technology for future memory systems. Generally, NVMMs have many desirable properties …

Brain-inspired hyperdimensional computing for ultra-efficient edge ai

H Amrouch, M Imani, X Jiao… - 2022 International …, 2022 - ieeexplore.ieee.org
Hyperdimensional Computing (HDC) is rapidly emerging as an attractive alternative to
traditional deep learning algorithms. Despite the profound success of Deep Neural Networks …

Multi-retention stt-mram architectures for iot: Evaluating the impact of retention levels and memory mapping schemes

B Jahannia, SA Ghasemi, H Farbeh - IEEE Access, 2024 - ieeexplore.ieee.org
In recent years, the energy consumption of IoT edge nodes has significantly increased due
to the communication process. This necessitates the need to offload more computation to the …

Reuse of off-the-shelf components in C2-style architectures

N Medvidovic, P Oreizy, RN Taylor - Proceedings of the 19th …, 1997 - dl.acm.org
Reuse of large-grain software components offers the potential for significant savings in
application development cost and time. Successful comuonent reuse and substitutability …

HALLS: An energy-efficient highly adaptable last level STT-RAM cache for multicore systems

K Kuan, T Adegbija - IEEE Transactions on Computers, 2019 - ieeexplore.ieee.org
Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to
SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high …

Hybrid drowsy SRAM and STT-RAM buffer designs for dark-silicon-aware NoC

J Zhan, J Ouyang, F Ge, J Zhao… - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
The breakdown of Dennard scaling prevents us from powering all transistors
simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work …