For more than four decades, transistors have been shrinking exponentially in size, and
therefore the number of transistors in a single microelectronic chip has been increasing …

This review paper explores considerations for ultimate CMOS transistor scaling. Transistor
architectures such as extremely thin silicon-on-insulator and FinFET (and related …

This paper demonstrates gate-all-around (GAA) n-and p-FETs on a silicon-on-insulator
with/spl les/5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift …

The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm
CMOS technology node. These nonplanar devices suffer from a high parasitic resistance …

The paradigm and the usage of CMOS are changing, and so are the requirements at all
levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and …

This paper reviews the status of research in modeling and simulation of single-event effects
(SEE) in digital devices and integrated circuits, with a special emphasis on the current …

In this letter, the electrostatic and the performance of cylindrical silicon nanowire (NW)
MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated. The …

(57) ABSTRACT A semiconductor chip includes a semiconductor Substrate 126, in which
first and second active regions are disposed. A resistor 124 is formed in the first active …

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs
reveals an interesting tradeoff in the analog/RF design space. It is found that FinFETs …