Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow‐Power Applications
R Vaddi, S Dasgupta, RP Agarwal - VLSI Design, 2009 - Wiley Online Library
In recent years, subthreshold operation has gained a lot of attention due to ultra low‐power
consumption in applications requiring low to medium performance. It has also been shown …
consumption in applications requiring low to medium performance. It has also been shown …
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic
R Vaddi, S Dasgupta, RP Agarwal - Microelectronics Journal, 2010 - Elsevier
Double gate FinFETs are shown to be better candidates for subthreshold logic design than
equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be …
equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be …
Subthreshold Transistors: Concept and Technology
BMM Tripathi - Advanced Ultra Low‐Power Semiconductor …, 2023 - Wiley Online Library
The continuous downscaling of Si MOS transistors facilitated technology to follow Moor's
Law which states that transistor density doubles every 18 months. However, the fundamental …
Law which states that transistor density doubles every 18 months. However, the fundamental …
Subthreshold circuits: Design, implementation and application
H Kanitkar - 2008 - repository.rit.edu
Digital circuits operating in the subthreshold region of the transistor are being used as an
ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design …
ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design …
Design and analysis of sub-DT sub-domino logic circuits for ultra low power applications
In this paper, we propose three dynamic threshold Sub-Domino circuit design schemes. The
performance of conventional Sub-domino logic and three proposed dynamic threshold Sub …
performance of conventional Sub-domino logic and three proposed dynamic threshold Sub …
On the road towards robust and ultra low energy CMOS digital circuits using sub/near threshold power supply
Y Pu - 2009 - research.tue.nl
Voltage scaling is one of the most effective and straightforward means for CMOS digital
circuit's energy reduction. Aggressive voltage scaling to the near or sub-threshold region …
circuit's energy reduction. Aggressive voltage scaling to the near or sub-threshold region …
操作於次臨界電壓區之數位動態電壓調整系統
林佳宏， 蘇朝琴 - 2010 - ir.lib.nycu.edu.tw
本論文提出一個動態電壓調整系統(Dynamic Voltage Scaling), 我們藉由動態的調整數位電路上
的工作電壓來克服當數位電路操作於次臨界電壓時, 製程與溫度的變化對數位電路工作頻率造成 …
的工作電壓來克服當數位電路操作於次臨界電壓時, 製程與溫度的變化對數位電路工作頻率造成 …
Minimum energy point of sub-threshold operated pass-transistor circuits
A Pajkanovic, TJ Kazmierski… - Proceeding of the 2012 …, 2012 - ieeexplore.ieee.org
In systems such as energy-harvester powered wireless sensors, energy consumption is the
most important design concern. Thus the initial design point is moved from minimum delay to …
most important design concern. Thus the initial design point is moved from minimum delay to …
Методика проведения оперативного анализа электрических и временных параметров цифровых КМОП элементов и СБИС на их основе
ВМ Дьяконов, НВ Семученков… - Известия …, 2012 - cyberleninka.ru
В статье приведена методика оперативного расчета электрических и временных
параметров цифровых схем, спроектированных на основе КМОП транзисторов …
параметров цифровых схем, спроектированных на основе КМОП транзисторов …