Modern processors are using increasingly larger sized on-chip caches. Also, with each
CMOS technology generation, there has been a significant increase in their leakage energy …

The end of Dennard scaling has made all systemsenergy-constrained. For data-intensive
applications with limitedtemporal locality, the major energy bottleneck is data …

As computation becomes increasingly limited by data movement and energy consumption,
exploiting locality throughout the memory hierarchy becomes critical to continued …

The energy constraints due to the end of Dennard scaling, the popularity of in-memory
analytics, and the advances in 3D integration technology have led to renewed interest in …

Die-stacked DRAM is a technology that will soon be integrated in high-performance
systems. Recent studies have focused on hardware caching techniques to make use of the …

Applications extensively use data objects with a regular and fixed layout, which leads to the
recurrence of access patterns over memory regions. Spatial data prefetching techniques …

Recent research advocates large die-stacked DRAM caches in many core servers to break
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …

This paper analyzes the trade-offs in architecting stacked DRAM either as part of main
memory or as a hardware-managed cache. Using stacked DRAM as part of main memory …

Recent trends of increasing core-count and memory/bandwidth-wall have led to major
overhauls in chip architecture. In face of increasing cache capacity demands, researchers …

Big-data server applications frequently encounter data misses, and hence, lose significant
performance potential. One way to reduce the number of data misses or their effect is data …