An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is
implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ …

This article reviews design challenges for low-power CMOS high-speed analog-to-digital
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …

This paper proposes an opamp-free solution to implement single-phase-clock controlled
noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal …

A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-
leakage digital process. A background bit-weight calibration exploiting the comparator …

This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed
architectural tradeoffs thanks to the use of ring amplification and background calibration. It …

This paper demonstrates a multi-bit/cycle successive-approximation register (SAR) analog-
to-digital converter (ADC) architecture for low-power and high-speed operation. The …

Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital
converters (ADCs) is remarkable in terms of architecture and performance. Because of the …

This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-
sampling receiver that employs a digital-mixing background timing mismatch calibration to …

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation
register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the …

This article presents a 7-bit 900-MS/s multi-bit/cycle successive approximation register
(SAR) analog-to-digital converter (ADC) with background offset calibration. Unlike prior …