Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review
Low-dropout (LDO) voltage regulator has fascinated industry professionals and academia
for the past few decades, and this trend is expected to continue in the coming years. The …
for the past few decades, and this trend is expected to continue in the coming years. The …
An output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector
This article presents a synthesizable digital low-dropout regulator (DLDO) that precludes the
use of an output load capacitor. For efficient regulation, the DLDO consists of fine and …
use of an output load capacitor. For efficient regulation, the DLDO consists of fine and …
A 0.5-V fully synthesizable SAR ADC for on-chip distributed waveform monitors
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-
to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system …
to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system …
Architectural advancement of digital low-dropout regulators
Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient fine-
grained power delivery and management in system-on-chips (SoCs) due to their process …
grained power delivery and management in system-on-chips (SoCs) due to their process …
A fast-transient 500-mA digitally assisted analog LDO with 30-μ V/mA load regulation and 0.0073-ps FoM in 65-nm CMOS
This article proposes a digitally assisted analog low-dropout (DA-ALDO) regulator, a hybrid
solution which realizes tight regulation, wide load current range, area-efficient power …
solution which realizes tight regulation, wide load current range, area-efficient power …
A residue-current-locked hybrid low-dropout regulator supporting ultralow dropout of sub-50 mV with fast settling time below 10 ns
This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an
ultralow dropout and a highly improved transient response. This HLDO incorporates a …
ultralow dropout and a highly improved transient response. This HLDO incorporates a …
Output-capacitorless tri-loop digital low dropout regulator achieving 99.91% current efficiency and 2.87 fs FOM
This article presents an output-capacitorless digital low-dropout regulator (OCL-DLDO) for
fine-grained on-chip power delivery and management in system-on-chip devices. The …
fine-grained on-chip power delivery and management in system-on-chip devices. The …
A highly synthesizable 0.5-to-1.0-V digital low-dropout regulator with adaptive clocking and incremental regulation scheme
This brief presents a highly synthesizable digital low-dropout regulator (DLDO) based on
adaptive clocking and an incremental regulation scheme. With these features, the clock …
adaptive clocking and an incremental regulation scheme. With these features, the clock …
A Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO with Time-Based Load-State Decision and Asynchronous Recovery
This article presents an external-clock-free fully synthesizable digital low-dropout regulator
(DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based …
(DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based …
A Self-Triggered Digitally Assisted Hybrid LDO with 110 ns Settling Time in 65 nm CMOS
This article presents a self-triggered digitally assisted hybrid low-dropout regulator (LDO).
The proposed architecture uses an analog LDO for steady-state operation and a digital LDO …
The proposed architecture uses an analog LDO for steady-state operation and a digital LDO …