Influences of source/drain extension region on thermal behavior of stacked nanosheet FET

S Srivastava, S Panwar, M Shashidhara… - … on Electron Devices, 2024 - ieeexplore.ieee.org
A well-calibrated numerical-simulation-based study reveals that an elongated extension
region can be a notable approach for the self-heating mitigation of nanosheet FETs. It is …

Optimization of Multi-fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression

C Yalung, W Yamwong, D Tantraviwat - IEEE Access, 2024 - ieeexplore.ieee.org
Despite advancements in mitigating the short channel effect using high-k materials, multi-
gate structures, and silicon-germanium (SiGe) alloys in three-dimensional FinFETs …

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

S Rai, R Sharma, R Saha, B Bhowmick… - Physica …, 2024 - iopscience.iop.org
In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG)
nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap …

Impact of S/D Extension Length and Sheet Stacking on Transient Behavior of Nanosheet FETs

S Srivastava, S Doge, S Panwar… - … on Circuits and …, 2024 - ieeexplore.ieee.org
The impact of source/drain extension length (LEXT) and vertical sheet stacking on the
transient response of the inverter, made up of nanosheet FETs, has been investigated. This …