Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …

Continuous learning faces the challenge of catastrophic forgetting. Our research findings
indicate that in unsupervised federated continual learning (UFCL), the limited model …

The growing IC complexity has led to a compelling need for design efficiency improvement
through new electronic design automation (EDA) methodologies. In recent years, many …

While Federated Learning (FL) offers a privacy guarantee as a promising distributed
learning paradigm, the robustness and efficiency issues hinder the practice of FL on …

The growing integrated circuit complexity has led to a compelling need for design efficiency
improvement through new electronic design automation (EDA) methodologies. In recent …

Abstract Design rule checking (DRC) clean is a fundamental chip manufacturing
requirement. However, achieving this is increasingly challenging with the advance of …

For hierarchical, building-block design methodologies, floorplanning is a crucial physical
design stage. As the size of the circuit grows, so does the intricacy of the circuitrises. To deal …

Over the years, the exponential increase in the complexity of chip design and the shrinking
of complementary metal-oxide semiconductor (CMOS) technology scaling have presented …