Parallel programming for FPGAs
This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-
specific FPGA systems. Our goal is to give the reader an appreciation of the process of …
specific FPGA systems. Our goal is to give the reader an appreciation of the process of …
Leveraging modern c++ in high-level synthesis
High-level synthesis (HLS) enables the automated conversion of high-level language
algorithms into synthesizable register-transfer level code, allowing computation-intensive …
algorithms into synthesizable register-transfer level code, allowing computation-intensive …
Resolve: Generation of high-performance sorting architectures from high-level synthesis
Field Programmable Gate Array (FPGA) implementations of sorting algorithms have proven
to be efficient, but existing implementations lack portability and maintainability because they …
to be efficient, but existing implementations lack portability and maintainability because they …
Real-time energy efficient hand pose estimation: A case study
The estimation of human hand pose has become the basis for many vital applications where
the user depends mainly on the hand pose as a system input. Virtual reality (VR) headset …
the user depends mainly on the hand pose as a system input. Virtual reality (VR) headset …
Module-per-Object: a human-driven methodology for C++-based high-level synthesis design
JS da Silva, FR Boyer… - 2019 IEEE 27th Annual …, 2019 - ieeexplore.ieee.org
High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware
design. However, achieving the highest Quality-of-Results (QoR) with HLS is still …
design. However, achieving the highest Quality-of-Results (QoR) with HLS is still …
PynqCopter-an open-source FPGA overlay for UAVs
B Cain, Z Merchant, I Avendano… - … Conference on Big …, 2018 - ieeexplore.ieee.org
FPGAs are a computing platform that excel in performing signal processing, control,
networking, and security in a high performance and power efficient manner. This makes …
networking, and security in a high performance and power efficient manner. This makes …
A Resource-Efficient Multi-Function Embedded Eye Tracker System Implemented on FPGA
In this paper, a multi-function embedded eye tracker system (ETS) has been presented and
FPGA implementation of that has been described. The image processing algorithm is based …
FPGA implementation of that has been described. The image processing algorithm is based …
FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach
FPGA technology can offer significantly hi\-gher performance at much lower power
consumption than is available from CPUs and GPUs in many computational problems …
consumption than is available from CPUs and GPUs in many computational problems …
2: Accelerator synthesis using algorithmic skeletons for rapid design space exploration
S Fernando, M Wijtvliet, C Nugteren… - … , Automation & Test …, 2015 - ieeexplore.ieee.org
Hardware accelerators in heterogeneous multiprocessor system-on-chips are becoming
popular as a means of meeting performance and energy efficiency requirements of modern …
popular as a means of meeting performance and energy efficiency requirements of modern …
An efficient FPGA overlay for MPI-2 RMA parallel applications
ML Mba, RCGN Ewo, J Denoulet… - 2022 20th IEEE …, 2022 - ieeexplore.ieee.org
Design productivity issues, including difficult hardware design and long compile times, are
major barriers to the widespread adoption of FPGA-based accelerations in main-stream …
major barriers to the widespread adoption of FPGA-based accelerations in main-stream …