Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to
reduce the diameter, latency, and cost of interconnection networks. High-radix networks …

Numerous studies have shown that datacenter computers rarely operate at full utilization,
leading to a number of proposals for creating servers that are energy proportional with …

Increasing integrated-circuit pin bandwidth has motivateda corresponding increase in the
degree or radix of interconnection networksand their routers. This paper introduces the …

With the trend towards increasing number of cores in chip multiprocessors, the on-chip
interconnect that connects the cores needs to scale efficiently. In this work, we propose the …

Future many-core processors will require high-performance yet energy-efficient on-chip
networks to provide a communication substrate for the increasing number of cores. Recent …

In the push to achieve exascale performance, systems will grow to over 100,000 sockets, as
growing cores-per-socket and improved single-core performance provide only part of the …

Due to wire delay scalability and bandwidth limitations inherent in shared buses and
dedicated links, packet-switched on-chip interconnection networks are fast emerging as the …

In this paper, we introduce the Tensor Streaming Processor (TSP) architecture, a functionally-
sliced microarchitecture with memory units interleaved with vector and matrix deep learning …

Large-scale training is important to ensure high performance and accuracy of machine-
learning models. At Facebook we use many different models, including computer vision …

Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D)
chip structures are envisioned as a viable solution to skyrocketing transistor densities and …