A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 20-GHz PLL with 20.9-fs random jitter
Y Zhao, M Forghani, B Razavi - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …
A 0.2-V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0-dBm output and 5.2-nW sleep power in 28-nm CMOS
This paper reports an ultralow-voltage (ULV) energy-harvesting bluetooth low-energy (BLE)
transmitter (TX). It features: 1) a fully integrated micropower manager (PM) to customize the …
transmitter (TX). It features: 1) a fully integrated micropower manager (PM) to customize the …
A Type-I Sub-Sampling PLL With a Footprint and −255-dB FOM
A Sharkia, S Mirabbasi… - IEEE Journal of Solid-State …, 2018 - ieeexplore.ieee.org
A dual-loop LC-voltage-controlled oscillator (VCO) based frequency synthesizer, composed
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
of an all-digital frequency-locked loop (ADFLL) and a voltage-mode, type-I, subsampling …
A 2.5–5.75-GHz ring-based injection-locked clock multiplier with background-calibrated reference frequency doubler
A Elkholy, D Coombs, RK Nandwana… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is
presented. It employs a background-calibrated reference frequency doubler to increase the …
presented. It employs a background-calibrated reference frequency doubler to increase the …
A harmonic-mixing PLL architecture for millimeter-wave application
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by
the invariably large closed-loop gain and the high operation frequency of the voltage …
the invariably large closed-loop gain and the high operation frequency of the voltage …
A low-jitter ring-oscillator phase-locked loop using feedforward noise cancellation with a sub-sampling phase detector
Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip
applications for their compactness and tuning range, but suffer from high jitter and supply …
applications for their compactness and tuning range, but suffer from high jitter and supply …
A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs
This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL)
featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the …
featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …