Antenna in embedded wafer-level ball-grid array package
K Liu, Y Lin - US Patent 9,806,040, 2017 - Google Patents
A semiconductor device has a semiconductor die and an encapsulant deposited over the
semiconductor die. A first conductive layer is formed with an antenna over a first surface of …
semiconductor die. A first conductive layer is formed with an antenna over a first surface of …
Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
WS Liao, CP Jou, FW Kuo - US Patent 9,711,465, 2017 - Google Patents
An integrated fan-out package having a top-side redistribu tion wiring structure, a back-side
redistribution wiring layer, a ground plane provided in the back-side redistribution wiring …
redistribution wiring layer, a ground plane provided in the back-side redistribution wiring …
Antenna in embedded wafer-level ball-grid array package
PC Marimuthu, ACB Yong, AK Oo, Y Lin - US Patent 10,636,753, 2020 - Google Patents
A semiconductor device has a semiconductor die and an encapsulant deposited over the
semiconductor die. A first conductive layer is formed with an antenna over a first surface of …
semiconductor die. A first conductive layer is formed with an antenna over a first surface of …
Structure and method for integrated circuits packaging with increased density
CG Woychik, AR Sitaram, A Cao, BS Lee - US Patent 10,381,326, 2019 - Google Patents
(57) ABSTRACT A method of forming a semiconductor package comprises forming one or
more first vias in a first side of a substrate and attaching a first side of a first microelectronic …
more first vias in a first side of a substrate and attaching a first side of a first microelectronic …
Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
WS Liao, CP Jou, FW Kuo - US Patent 9,991,216, 2018 - Google Patents
A method for forming an integrated fan-out package includes depositing an adhesive layer
on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side …
on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side …
Antenna in embedded wafer-level ball-grid array package
K Liu, Y Lin - US Patent 10,211,171, 2019 - Google Patents
Associates, PC (57) ABSTRACT A semiconductor device has a semiconductor die and an
encapsulant deposited over the semiconductor die. A first conductive layer is formed with an …
encapsulant deposited over the semiconductor die. A first conductive layer is formed with an …
BVA interposer
T Caskey, I Mohammed, CE Uzoh… - US Patent …, 2019 - Google Patents
ABSTRACT A method for making an interposer includes forming a plurality of wire bonds
bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed …
bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed …
Microelectronic package for wafer-level chip scale packaging with fan-out
AS Prabhu, R Katkar - US Patent 10,181,457, 2019 - Google Patents
Int. CI. HOIL 23/00(2006. 01) HOIL 23 31(2006. 01)(Continued)(52) US CI. CPC....... HOIL
25/105 (2013. 01); HOIL 21/4846 (2013. 01); HOIL 21/4885 (2013. 01); HOIL 23/3128 (2013 …
25/105 (2013. 01); HOIL 21/4846 (2013. 01); HOIL 21/4885 (2013. 01); HOIL 23/3128 (2013 …
Embedded wire bond wires
AS Prabhu, A Awujoola, W Zohni, W Subido - US Patent 10,490,528, 2019 - Google Patents
Apparatuses relating generally to a vertically integrated microelectronic package are
disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface …
disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface …
Wire bond wires for interference shielding
A Awujoola, Z Sun, W Zohni, AS Prabhu… - US Patent …, 2018 - Google Patents
Apparatuses relating generally to a microelectronic package having protection from
interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a …
interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a …