Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
Recent advances and trends in voltage-time domain hybrid ADCs
Y Zhang, Z Zhu - IEEE Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
The benefits of technology scaling have fueled interest in voltage-time domain hybrid ADCs.
The hybrid ADCs employing combinations of successive approximation register (SAR), time …
The hybrid ADCs employing combinations of successive approximation register (SAR), time …
A 0.6-V 13-bit 20-MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques
This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-
assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this …
assisted successive approximation register (SAR) analog-to-digital converter (ADC). In this …
An 8-bit 10-GS/s 16× interpolation-based time-domain ADC with< 1.5-ps uncalibrated quantization steps
This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves 10
GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0 …
GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0 …
A 0.5–1.1-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator
A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-
controlled oscillator (VCO)-based comparator is presented in this paper. The relationship …
controlled oscillator (VCO)-based comparator is presented in this paper. The relationship …
A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS
C Zhang, A Hu, D Liu, S Ma, H Li, Z Jin, J Liu… - Microelectronics …, 2023 - Elsevier
This paper presents an energy efficient two-step hybrid-domain successive approximation
register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback …
register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback …
A 12-bit 260-MS/s pipelined-SAR ADC with ring-TDC-based fine quantizer for automatic cross-domain scale alignment
H Zhao, FF Dai - IEEE Journal of Solid-State Circuits, 2023 - ieeexplore.ieee.org
This article presents a power efficient and process, voltage, and temperature (PVT) robust
pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that …
pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that …
All-digital successive approximation TDC in time-mode signal processing
The need for low-power high-resolution ADCs in a broad range of emerging applications
and the architecture to realize these ADCs are examined. The pros and cons of various TDC …
and the architecture to realize these ADCs are examined. The pros and cons of various TDC …
A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC
X Li, Y Liang - Microelectronics Journal, 2023 - Elsevier
This paper proposes a reconfigurable and energy-efficient 8-to-12-bit 10 MS/s analog-to-
digital-converter (ADC), which adopts the SAR-TDC architecture to enhance the power …
digital-converter (ADC), which adopts the SAR-TDC architecture to enhance the power …
A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS
Z Yu, Y Liang, S Liu - Microelectronics Journal, 2021 - Elsevier
This paper proposes a second-order sigma-delta two-step hybrid-domain ADC comprises of
a SAR ADC, a voltage-to-time converter (VTC), and a second-order sigma-delta TDC with all …
a SAR ADC, a voltage-to-time converter (VTC), and a second-order sigma-delta TDC with all …